A 1Tb 4b/Cell 96-Stacked-WL 3D NAND Flash Memory with 30MB/s Program Throughput Using Peripheral Circuit Under Memory Cell Array Technique pairs for low input offset to reduce a random dopant fluctuation. In order to reduce an input offset, the error amplifier designs that DC gain is above 74dB with all PVT variations. The Monte-Carlo simulation shows the variation is decreased by 46.9%, comparing to conventional one.

📋 论文概要

本文提出了一款1Tb容量、4b/cell（QLC）的96层堆叠字线3D NAND闪存，通过将外围电路置于存储阵列下方（PUC技术）实现了30MB/s的编程吞吐量。该设计有效解决了位线间耦合噪声导致的感测精度下降和Vth窗口展宽问题。

💡 主要创新点

• 采用96层堆叠字线（WL）和4b/cell（QLC）技术，实现1Tb高密度存储。
• 将外围电路置于存储阵列下方（Peripheral Circuit Under Memory Cell），优化芯片面积并提升编程吞吐量至30MB/s。
• 针对位线耦合噪声问题，通过改进感测电路和I-trip曲线设计，提高感测精度并缩小Vth窗口。

🏷 关键词

📄 原文摘要

Sunghwa Ok, Jongwoo Kim, Kayoung Cho, Hyunchul Lee, Geonu Kim, Kangwoo Park, Kwanho Kim, Heejoo Lee, Sooyeol Chai, Chankeun Kwon, Hanna Cho, Chanhui Jeong, Yujin Yang, Jayoon Goo, Jangwon Park, Juhyeong Lee, Heonki Kim, Kangwook Jo, Cheoljoong Park, Hyeonsu Nam, Hyunseok Song, Sangkyu Lee, Woopyo Jeong, Kun-Ok Ahn, Tae-Sung Jung It is known that BL-coupling noise between neighboring BLs diminishes the accuracy in a sensing operation, and thus it broadens Vth windows. Figure 13.2.3(d) displays the curve of I-trip, cell current to discriminate whether the cell is turned on or off, responding to both adjacent BL patterns and the threshold voltage of the cell. When adjacent BLs (aggressors) are grounded, I-trip of victim BL holds its value without coupling noise in a sensing operation. However, I-trip of victim BL fluctuates due to coupling noise when the adjacent BLs are precharged. If the states of adjacent BLs are controlled to ground levels during a

👥 作者与机构

Hwang Huh, Wanik Cho, Jinhaeng Lee, Yujong Noh, Yongsoon Park,