ISSCC 2017
Session 3
Digital Processors
A 10nm FinFET 2.8GHz Tri-Gear Deca-Core CPU Complex with Optimized Power-Delivery Network for Mobile SoC Performance
Sumanth Gururajarao1, Rolf Lagerquist1, Jin Son1, Gordon Gammie1, Gordon Lin2, Achuta Thippana1, Kent Li1, Manzur Rahman1, Wuan Kuo2, David Yen2, Yi-Chang Zhuang2, Ue Fu2, Hung-Wei Wang2, Mark Peng3, Cheng-Yuh Wu2, Taner
ISSCC 2017
Session 3
Digital Processors
A 14nm 1GHz FPGA with 2.5D Transceiver Integration
Kok Hong Chan1, Andy Tong1, Sean Atsatt1, Dana How1, Peter McElheny1, Keith Duwel1, Jeffrey Schulz1, Darren Faulkner3, Gopal Iyer1, George Chen1, Hee Kong Phoon4, Han Wooi Lim4, Wei-Yee Koay4, Ty Garibay3 Intel, San Jose
ISSCC 2017
Session 3
Digital Processors
Zen: A Next-Generation High-Performance x86 Core
Shane Southard1, Hugh McIntyre3, Amy Novak1, Stephen Kosonocky2, Ravi Jotwani1, Alex Schaefer1, Edward Chang2, Joshua Bell1, Michael Co1 AMD, Austin, TX AMD, Fort Collins, CO 3 AMD, Sunnyvale, CA 1 2 Codenamed “Zen”, AMD
ISSCC 2017
Session 3
Digital Processors
POWER9TM: A Processor Family Optimized for Cognitive Computing with 25Gb/s Accelerator Links and 16Gb/s PCIe Gen4
Rahul Rao3, Jose Paredes2, Michael Floyd2, Michael Sperling4, Ryan Kruse2, Vinod Ramadurai2, Ryan Nett2, Saiful Islam2, Juergen Pille5, Donald Plass4 IBM, Yorktown Heights, NY IBM, Austin, TX 3 IBM, Bangalore, India 4 IB
ISSCC 2017
Session 26
Digital Processors
Adaptive Clocking in the POWER9TM Processor for Voltage Droop Protection
Pawel Owczarczyk3, Eric J. Fluhr1, Joshua Friedrich1, Paul Muench3, Timothy Diemoz3, Pierce Chuang2, Christos Vezyrtzis2 IBM, Austin, TX IBM, Yorktown Heights, NY 3 IBM, Poughkeepsie, NY 1 2 Increasing transistor counts
ISSCC 2017
Session 26
Digital Processors
A 0.4-to-1V 1MHz-to-2GHz Switched-Capacitor Adiabatic Clock Driver Achieving 55.6% Clock Power Reduction
Clock distribution in modern SoCs consumes a significant fraction of total chip power. To reduce clock distribution power, resonant clocking schemes, where an inductive reactance is used to cancel the capacitive reactanc
ISSCC 2017
Session 26
Digital Processors
Reconfigurable Clock Networks for Random Skew Mitigation from Subthreshold to Nominal Voltage
Clock network optimization is substantially affected by the operating voltage VDD, as the clock skew is dominated by different mechanisms and has a different balance between wire and repeater delay at different VDD (Fig.
ISSCC 2017
Session 26
Digital Processors
Power Supply Noise in a 22nm z13TM Microprocessor
Richard Rizzolo3, Tobias Webel4, Thomas Strach4, Otto Torreiter4, Preetham Lobo5, Alper Buyuktosunoglu1, Ramon Bertran1, Michael Floyd6, Malcolm Ware6, Gerard Salem7, Sean Carey8, Phillip Restle1 IBM Research, Yorktown H
ISSCC 2017
Session 21
Digital Processors
An Actively Detuned Wireless Power Receiver with Public Key Cryptographic Authentication and Dynamic Power Allocation
they replace Point-Doubling with an essentially free Frobenius Endomorphism [7]. Efficient micro-coding and a Serial Input Parallel Output (SIPO) finite field multiplier ensure that only 2 additional registers (t, z) are
ISSCC 2017
Session 21
Digital Processors
2pJ/MAC 14b 8×8 Linear Transform Mixed-Signal Spatial Filter in 65nm CMOS with 84dB Interference Suppression
machine learning (ML) and the internet-of-things (IoT) have resulted in a renewed interest in analog matrix-vector multiplication (MvM) accelerators [1-3]. Classification based tasks have exploited low-to-medium resoluti
ISSCC 2017
Session 21
Digital Processors
A 12nW Always-On Acoustic Sensing and Object Recognition Microsystem Using Frequency-Domain Feature Extraction and SVM Classification
increasingly intelligent and context-aware. Sound is an attractive sensory modality because it is information-rich but not as computationally demanding as alternatives such as vision. New applications of ultra-low power
ISSCC 2017
Session 21
Digital Processors
A 3-to-5V Input 100Vpp Output 57.7mW 0.42% THD+N Highly Integrated Piezoelectric Actuator Driver
Piezoelectric actuators are used in a growing range of applications, e.g., haptic feedback systems, cooling fans, and microrobots. However, to fully realize their potential, these actuators require drivers able to effici
ISSCC 2017
Session 21
Digital Processors
A Reduced-Order Sliding-Mode Controller with an Auxiliary PLL Frequency Discriminator for Ultrasonic Electric Scalpels
Intel, Hillsboro, OR 1 2 Piezoelectric transducer (PT) is an emerging energy-based technology for electrosurgery. With proper driving signals, the PT is utilized as an electric scalpel as shown in Fig. 21.4.1. It convert
ISSCC 2017
Session 21
Digital Processors
A Sub-mm3 Wireless Implantable Intraocular Pressure Monitor Microsystem
intraocular pressure (IOP) in the anterior chamber of the eye can damage the optic nerve causing irreversible blindness [1]. An IOP monitoring microsystem (IMM) implanted in the interior chamber of the eye is required to
ISSCC 2017
Session 21
Digital Processors
A 1.4mΩ-Sensitivity 94dB-Dynamic-Range Electrical Impedance Tomography SoC and 48-Channel Hub SoC for 3D Lung Ventilation Monitoring System
ventilation because it is the only real-time lung imaging method without large equipment [1-2]. However, previous EIT systems just provided 2D cross-sectional image with limited spatial information of the lung and unnegl
ISSCC 2017
Session 21
Digital Processors
Nanowatt Circuit Interface to Whole-Cell Bacterial Sensors
emerging as a platform for small molecule detection in challenging environments [1]. A key barrier to widespread deployment of autonomous bacterial sensors is the detection of low-level bioluminescence, which is typicall
ISSCC 2017
Session 14
Digital Processors
A 135mW Fully Integrated Data Processor for Next-Generation Sequencing
National Chiao Tung University, Hsinchu, Taiwan 1 2 DNA sequencing is the process of determining the precise order of nucleotides (A, C, G, T) within a DNA molecule and is now indispensable for genetics and medical resea
ISSCC 2017
Session 14
Digital Processors
A 288μW Programmable Deep-Learning Processor with 270KB On-Chip Weight Storage Using Non-Uniform Memory Hierarchy for Mobile Intelligence
Qing Dong1, Yen-Po Chen1, Laura Fick1, Xun Sun1, Ron Dreslinski1, Trevor Mudge1, Hun Seok Kim1, David Blaauw1, Dennis Sylvester1 University of Michigan, Ann Arbor, MI CubeWorks, Ann Arbor, MI 1 2 Deep learning has proven
ISSCC 2017
Session 14
Digital Processors
A 0.62mW Ultra-Low-Power Convolutional-NeuralNetwork Face-Recognition Processor and a CIS Integrated with Always-On Haar-Like Face Detector
for the next-generation UI/UX of wearable devices. A FR system, shown in Fig. 14.6.1, was developed as a life-cycle analyzer or a personal black box, constantly recording the people we meet, along with time and place inf
ISSCC 2017
Session 14
Digital Processors
A Scalable Speech Recognizer with Deep-NeuralNetwork Acoustic Models and Voice-Activated Power Gating
Analog Devices, Cambridge, MA 1 Previous work such as [4] provided micropower VADs that can be used in quiet environments or in applications that tolerate false alarms. In our application, false alarms will unnecessarily
ISSCC 2017
Session 14
Digital Processors
A 28nm SoC with a 1.2GHz 568nJ/Prediction Sparse Deep-Neural-Network Engine with >0.1 Timing Error Rate Tolerance for IoT Applications
(IoT) devices with the capability to interpret the complex, noisy real-world data arising from sensorrich systems. Achieving sufficient energy efficiency to execute ML workloads on an edge-device necessitates specialized
ISSCC 2016
Session 4
Digital Processors
A 65nm ReRAM-Enabled Nonvolatile Processor with 6× Reduction in Restore Time and 4× Higher Clock Frequency Using Adaptive Data Retention and Self-Write-Termination Nonvolatile Logic
Zhe Yuan1, Chien-Chen Lin2, Qi Wei1, Yu Wang1, Ya-Chin King2, Chrong-Jung Lin2, Pedram Khalili3, Kang-Lung Wang3, Meng-Fan Chang2, Huazhong Yang1 Tsinghua University, Beijing, China, National Tsing Hua University, Hsinch
ISSCC 2016
Session 4
Digital Processors
A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V Shared Logarithmic Floating Point Unit for Acceleration of Nonlinear Function Kernels in a Tightly Coupled Processor Cluster
many application areas, such as IoT and wearables. While for some applications, integer and fixed-point processor instructions suffice, others (e.g. simultaneous localization and mapping – SLAM, stereo vision, nonlinear
ISSCC 2016
Session 4
Digital Processors
A 16nm FinFET Heterogeneous Nona-Core SoC Complying with ISO26262 ASIL-B: Achieving 10-7 Random Hardware Failures per Hour Reliability
car information systems (commonly referred to as car infotainment) is expanding from dedicated navigation systems to joint car-cockpit systems, including the dashboard meter, telematics for the internet/cloud, and advanc
ISSCC 2016
Session 4
Digital Processors
A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC for Car Information Systems
Chi Lan Phuong Nguyen2, Tetsuya Shibayama1, Kenichi Iwata1, Katsuya Mizumoto1, Takahiro Irita3, Hirotaka Hara3, Toshihiro Hattori1 Renesas System Design, Tokyo, Japan, Renesas Design Vietnam, Ho Chi Minh City, Vietnam, 3
ISSCC 2016
Session 4
Digital Processors
A 20nm 2.5GHz Ultra-Low-Power Tri-Cluster CPU Subsystem with Adaptive Power Allocation for Optimal Mobile SoC Performance
C.J. Chung1, Sumanth Gururajarao1, Ping Kao2, Anand Rajagopalan1, Anirban Saha3, Amit Jain4, Ericbill Wang2, Shichin Ouyang5, Huajun Wen1, Achuta Thippana1, HsinChen Chen1, Syed Rahman1, Minh Chau1, Anshul Varma1, Brian
ISSCC 2016
Session 4
Digital Processors
Increasing the Performance of a 28nm x86-64 Microprocessor Through System Power Management
Ravinder Rachala1, Sriram Sambamurthy1, Steven Liepe2, Miguel Rodriguez2, Tom Burd3, Adam Clark4, Michael Austin1, Samuel Naffziger2 AMD, Austin, TX, AMD, Fort Collins, CO, 3 AMD, Sunnyvale, CA, 4 AMD, Markham, ON, Canad
ISSCC 2016
Session 4
Digital Processors
14nm 6th-Generation Core Processor SoC with Low Power Consumption and Improved Performance
Muhammad Abozaed, Yair Talker, Ziv Shmuely, Saher Abu Rahme transitions in the victim neighborhood circuits should not exceed a crosstalk limit during normal operation. Another parameter that must be factored is reliabil
ISSCC 2015
Session 4
Digital Processors
A 28nm x86 APU Optimized for Power and Area Efficiency
Jim Farrell1, Dave Johnson2, Guhan Krishnan1, Hugh McIntyre3, Edward McLellan1, Samuel Naffziger2, Russell Schreiber4, Sriram Sundaram4, Jonathan White1 AMD, Boxborough, MA, 2AMD, Fort Collins, CO, 3 AMD, Sunnyvale, CA,
ISSCC 2015
Session 4
Digital Processors
A 409GOPS/W Adaptive and Resilient Domino Register File in 22nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection
Droop, Temperature and Aging Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo Aseron, Trang Nguyen Jr, Charles Augustine, James Tschanz, Vivek De Intel, Hillsboro, OR 8-transistor (8T) cell 1-read/1-write (1R1W) register file
ISSCC 2015
Session 4
Digital Processors
The Xeon® Processor E5-2600 v3: A 22nm 18-Core Product Family
Arvind Raghavan1, Charles Morganti2, Chris Houghton1, Dan Krueger2, Olivier Franza1, Jayen Desai2, Jason Crop2, Dave Bradley2, Chris Bostak2, Sal Bhimji1, Matt Becker1 Intel, Hudson, MA, 2Intel, Fort Collins, CO 1 The ne
ISSCC 2015
Session 4
Digital Processors
Energy-Efficient Microserver Based on a 12-Core 1.8GHz 188K-CoreMark 28nm Bulk CMOS 64b SoC for Big-Data Applications with 159GB/s/L Memory Bandwidth System Density
Huy N. Nguyen2, Mihir Pandya2 IBM Research, Rüschlikon, Switzerland, Freescale Semiconductor, Austin, TX 1 2 MicroServers integrate an entire server motherboard into a single Server-on-aChip (SoC), excluding DRAM, NOR-bo
ISSCC 2015
Session 4
Digital Processors
Fine-Grained Adaptive Power Management of the SPARC M7 Processor
Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang Oracle, Redwood Shores, CA The goal of the power management system of Oracle’s SPARC M7 CPU [1] is to maximize the performanc
ISSCC 2015
Session 4
Digital Processors
A 20nm 32-Core 64MB L3 Cache SPARC M7 Processor
Francis Schumacher, Venkat Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McA
ISSCC 2015
Session 4
Digital Processors
22nm Next-Generation IBM System z Microprocessor
Donald Plass2, Yuen Chan2, Sean Carey2, Gerard Salem4, Friedrich Schroeder5, Frank Malgioglio2, Guenter Mayer5, Christopher Berry2, Michael Wood2, Yiu-Hing Chan2, Mark Mayo2, John Isakson3, Charudhattan Nagarajan6, Tobia
ISSCC 2015
Session 23
Digital Processors
A Highly Integrated Smartphone SoC Featuring a 2.5GHz Octa-Core CPU with Advanced High-Performance and Low-Power Techniques
Ichiro Lin1, HsinChen Chen1, Wuan Kuo2, Anand Rajagopalan1, Wei-Zheng Ge1, Rolf Lagerquist1, Syed Rahman1, CJ Chung1, Simon Wang2, Lee-Kee Wong2, Yi-Chang Zhuang2, Kent Li1, Jidong Wang1, Minh Chau1, Yijing Liu1, Daniel
ISSCC 2015
Session 23
Digital Processors
A 1920×1080 30fps 611mW Five-View Depth-Estimation Processor for Light-Field Applications
essential in emerging computer vision applications. Although active sensing methods can provide an accurate indoor depth map, they have limited resolution and consume significant power, such as the 2.1W time-of-flight se
ISSCC 2015
Session 23
Digital Processors
20nm High-κ Metal-Gate Heterogeneous 64b Quad-Core CPUs and Hexa-Core GPU for High-Performance and Energy-Efficient Mobile Application Processor
Kwangil Kim, Ken Shin, Yohan Kwon, Heungchul Oh, Jaeyoung Lim, Dong-wook Lee, Jongho Lee, Inpyo Hong, Kyungkuk Chae, Heon-Hee Lee, Sung-Wook Lee, Seongho Song, Chung-Hee Kim, Jin-Soo Park, Heesoo Kim, Sunghee Yun, Uk-Rae
ISSCC 2015
Session 18
Digital Processors
A 2.4mm2 130mW MMSE-Nonbinary-LDPC Iterative Detector-Decoder for 4×4 256-QAM MIMO in 65nm CMOS
The latest multiple-input multiple-output (MIMO) wireless systems have adopted iterative detection and decoding (IDD) to reduce the signal-to-noise ratio (SNR) required for a reliable transmission. An IDD system consists
ISSCC 2015
Session 18
Digital Processors
A 0.5nJ/Pixel 4K H.265/HEVC Codec LSI for Multi-Format Smartphone Applications
Han-Liang Chou, Chih-Ming Wang, Tung-Hsing Wu, Hue-Min Lin, Yi-Hsin Huang, Chia-Yun Cheng, Ting-An Lin, Chun-Chia Chen, Yu-Kun Lin, Min-Hao Chiu, Wei-Cing Li, Sheng-Jen Wang, Yen-Chieh Lai, Ping Chao, Chih-Da Chien, Meng
ISSCC 2015
Session 18
Digital Processors
A Configurable 12-to-237KS/s 12.8mW Sparse-Approximation Engine for Mobile ExG Data Aggregation
University of California, Los Angeles, CA Compressive sensing (CS) is a promising solution for low-power on-body sensors for 24/7 wireless health monitoring [1]. In such an application, a mobile data aggregator performin
ISSCC 2015
Session 18
Digital Processors
A Matrix-Multiplying ADC Implementing a Machine-Learning Classifier Directly with Data Conversion
Embedded sensing systems conventionally perform A-to-D conversion followed by signal analysis. In many applications, the analysis of interest is inference (e.g., classification), but the sensor signals involved are too c
ISSCC 2015
Session 18
Digital Processors
A 0.5V 54µW Ultra-Low-Power Recognition Processor with 93.5% Accuracy Geometric Vocabulary Tree and 47.5% Database Compression
Microwatt object recognition is being considered for many applications, such as autonomous micro-air-vehicle (MAV) navigation, a vision-based wake-up or user authentication for the smartphones, and a gesture recognition-
ISSCC 2015
Session 18
Digital Processors
A 1.9TOPS and 564GOPS/W Heterogeneous Multicore SoC with Color-Based Object Classification Accelerator for Image-Recognition Applications
Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori Toshiba, Kawasaki, Japan Image recognition technologies have gained prominence in a variety o
ISSCC 2015
Session 18
Digital Processors
A 2.71nJ/Pixel 3D-Stacked Gaze-Activated Object-Recognition System for Low-Power Mobile HMD Applications
next-generation mainstream wearable devices. However, previous HMD systems [1] have had limited application, primarily due to their lacking a smart user interface (UI) and user experience (UX). Since HMD systems have a s
ISSCC 2015
Session 14
Digital Processors
A Sub-Sampling All-Digital Fractional-N Frequency Synthesizer with -111dBc/Hz In-Band Phase Noise and an FOM of -242dB
Seyed Arash Mirhaj1, Yen-Cheng Kuan1, Huan-Neng Chen2, Chewn-Pu Jou2, Ming-Hsien Tsai2, Fu-Lung Hsueh2, Mau-Chung Frank Chang1 University of California, Los Angeles, CA, 2TSMC, Hsinchu, Taiwan 1 The noise performance of
ISSCC 2015
Session 14
Digital Processors
A 0.009mm2 2.06mW 32-to-2000MHz 2nd-Order ΔΣ Analogous Bang-Bang Digital PLL with Feed-Forward Delay-Locked and Phase-Locked Operations in 14nm FinFET Technology
architectures, from a planar structure to a FinFET to achieve decreased leakage, further downscaling, and better sub-threshold slope, even under a lower power supply [1]. Downscaling trends have forced the analog semicon
ISSCC 2015
Session 14
Digital Processors
In-Situ Techniques for In-Field Sensing of NBTI Degradation in an SRAM Register File
SRAM register files have sensitive circuitry and often operate with high switching activity and at high temperature. This makes them particularly vulnerable to aging by negative-bias temperature instability (NBTI) degrad
ISSCC 2015
Session 14
Digital Processors
An All-Digital Power-Delivery Monitor for Analysis of a 28nm Dual-Core ARM Cortex-A57 Cluster
ARM, Cambridge, United Kingdom The current trend for System-on-Chip (SoC) compute subsystems is to improve energy efficiency, while operating at a similar power budget as previous generations. Reduced supply voltages and
ISSCC 2015
Session 14
Digital Processors
A 1.22ps Integrated-Jitter 0.25-to-4GHz Fractional-N ADPLL in 16nm FinFET CMOS
(ADPLLs) offer faster locking time, easier portability and better performance in advanced semiconductor processes as compared to analog PLLs. Advanced FinFET devices exhibit better gm and ION than planar devices [1], but