Digital Processors

proposed for a low-power, low-noise fractional-N frequency synthesizer. Among the various innovations, a reference-multiplied architecture offers distinct advantages compared to conventional DPLLs [1]. First, low quantiz

Physically unclonable functions (PUFs) enable information security down to the chip level [1-4]. Arrays of PUF bitcells (Fig. 14.3.1) generate chip-specific keys that are unpredictable, repeatable and cannot be measured

Security is a key concern in today’s mobile devices and a number of hardware implementations of security primitives have been proposed, including true random number generators, differential power attack avoidance, and ch

Systems-onChip (SoCs), which contain microprocessors, I/O interfaces, memories, power management, and communication systems. Fully synthesizable PLLs [1-2], designed using a pure digital design flow, have been proposed t

Thomas P. Thomas, Christopher Mozak, Brent Boswell, Manoj Lal, Anant Deval, Jonathan Douglas, Mahmoud Elassal, Ankireddy Nalamalpu, Timothy M. Wilson, Matthew Merten, Srinivas Chennupaty, Wilfred Gomes, Rajesh Kumar Inte

John Ngai, Russ Homer, Matthew Ashcraft, Greg Favor Applied Micro, Sunnyvale, CA Potenza is a first generation 64b ARM v8 processor and memory sub-system of the X-GeneTM server platform [1]. The Potenza processor module

Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De Intel, Hillsboro, OR

In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consum

Stephen Kosonocky2, Robert S. Orefice1, Donald A. Priore1, Jonathan White1, Kathryn Wilcox1 AMD, Boxborough, MA, 2AMD, Fort Collins, CO, 3AMD, Austin, TX 1 The AMD two-core x86-64 CPU module, codenamed “Steamroller”, con

dual-threaded 64b Ivybridge cores [1] and 37.5MB shared L3 cache. The system interface includes two on-chip memory controllers, each with two memory channels and supports multiple system topologies. The processor has 4.3

4IBM STG, Williston, VT, 5IBM STG, Raleigh, NC 1 3 A resonant-clock design for the IBM POWER8 processor core was implemented with 2 resonant modes (and a non-resonant mode), saving clock power over a wide frequency range

Gregory Still3, Ryan Kruse4, Seongwon Kim1, David Boerstler4, Tilman Gloekler5, Raphael Robertazzi1, Kevin Stawiasz1, Timothy Diemoz2, George English2, David Hui2, Paul Muench2, Joshua Friedrich4 IBM, Yorktown Heights, N

Gregory Still3, Christopher Gonzalez2, Allen Hall1, David Hogenmiller1, Frank Malgioglio4, Ryan Nett1, Jose Paredes1, Juergen Pille5, Donald Plass4, Ruchir Puri2, Phillip Restle2, David Shan1, Kevin Stawiasz2, Zeynep Top

David Blaauw, Dennis Sylvester locking the oscillation and impacting collapse event time. To measure noise amplitude on-chip, an asynchronous clock samples the supply voltage, compares it with an external reference volta

Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram K. Krishnamurthy, Vivek De Intel, Hillsboro, OR Physically unclonable function (PUF) circuits are low-cost cryptographic primitives used for generation

Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De Intel, Hillsboro, OR Energy-efficient networks-on-chip (NoCs) are key enablers for exa-scale computation by shifting power budge

Alberth Arvidsson1, Harald Bauer2, Kees van Berkel3, Joaquin Canovas1, Minh Do1, Anders Ekelund1, Torsten Larsson1, Bo Lincoln1, Magnus Malmberg1, Masao Naruse4, Masashi Onishi4, Christer Östberg1, Jean-Paul Smeets3, Mar

Erik Fischer, Steffen Kunze, Emil Matúš, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, Jens-Uwe Schlüßler, Stefan Scholze, Dennis Walter, René Schüffny Technisc

Mario Konijnenburg, Yan Zhang, Jan Stuyt, Maryam Ashouei, Guido Dolmans, Tobias Gemmeke, Harmke de Groot Holst Centre/imec, Eindhoven, The Netherlands Ultra-low-power (ULP), short-range wireless connectivity is becoming

Ayuka Morioka1, Kunihiko Ishihara1, Keizo Kinoshita2, Shunsuke Fukami2, Sadahiko Miura1, Naoki Kasai2, Tetsuo Endoh2, Hideo Ohno2, Takahiro Hanyu2, Tadahiko Sugibayashi1 NEC, Tsukuba, Japan, 2Tohoku University, Sendai, J

Processor Alice Wang1, Tsung-Yao Lin2, Shichin Ouyang3, Wei-Hung Huang2, Jidong Wang1, Shu-Hsin Chang2, Sheng-Ping Chen2, Chun-Hsiung Hu2, Jim C. Tai2, Koan-Sin Tan2, Meng-Nan Tsou2, Ming-Hsien Lee2, Gordon Gammie1, Chi-

Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori Renesas Electronics, Tokyo, Japan The worldwide demand f

Xufeng Chen2, Maen Alradaideh1, Tom Wernimont1, Kartik Ayyar3, Dan Bui1, Dwight Galbi1, Allan Lester1, Willie Anderson1 Qualcomm, Austin, TX, 2Qualcomm, San Diego, CA, Qualcomm, Bangalore, India 1 The pulsed latches, als

autonomic vehicle navigation, smart surveillance and unmanned air vehicles (UAVs) [1-3]. Most of the processors adopt a single classifier rather than multiple classifiers even though multi-classifier systems (MCSs) offer

University of Michigan, Ann Arbor, MI Recently, computer vision technologies are being applied to smaller systems such as cell phones, digital cameras, and unmanned surveillance platforms [1]. Feature extraction is a cri

photography [1], enable capture and synthesis of images that could not be captured with a traditional camera. Non-linear filtering techniques like bilateral filtering [2] form a significant part of computational photogra

(HEVC) [1] provides 50% improvement in coding efficiency compared to H.264/AVC, to meet the rising demand for video streaming, better video quality and higher resolutions. The coding gain is achieved using more complex t

Youngeun Park, Chunho Kim, Yunseok Choi, Jinhong Oh, Changhoon Oh, Gurnrack Moon, Sangduk Kim, Horang Jang, Jin-Aeon Lee, Chinhyun Kim, Sungho Park Samsung Electronics, Yongin, Korea 72.5GFLOPS GPGPU computing, 240 Mpixe

Po-Hao Wang3, Ting-Yu Shyu1, Chien-Yung Chou2, Shien-Chun Luo2, Jiun-In Guo3, Tien-Fu Chen3, Gene C.H. Chuang2, Yuan-Hua Chu2, Liang-Chia Cheng2, Hong-Men Su4, Chewnpu Jou5, Meikei Ieong5, Cheng-Wen Wu2, Jinn-Shyan Wang1

Kohei Wakahara1, Tsugio Matsuyama1, Keiji Hasegawa1, Toshiharu Saito1, Akira Fukuda1, Kaname Teranishi1, Kazuki Fukuoka2, Noriaki Maeda2, Koji Nii2, Takeshi Kataoka1, Toshihiro Hattori1 Renesas Mobile, Tokyo, Japan, Rene

Hoi-Jin Lee1, Dongjoo Seo1, Brian Millar2, Yohan Kwon1, Ravi Iyengar2, Min-Su Kim1, Ahsan Chowdhury2, Sung-Il Bae1, Inpyo Hong1, Wookyeong Jeong2, Aaron Lindner2, Ukrae Cho1, Keith Hawkins2, Jae Cheol Son1, Seung Ho Hwan

Sota Sakabayashi1, Yoichi Koyanagi2, Ryuji Iwatsuki1, Kazumi Hayasaka1, Taiki Uemura3, Gaku Ito1, Yoshitomo Ozeki1, Hiroyuki Adachi1, Kazuhiro Furuya1, Tsuyoshi Motokurumada1 Fujitsu, Kawasaki, Japan, 2Fujitsu Laboratori

Oracle, Santa Clara, CA, 2 Oracle, San Diego, CA 1 Continuous advancement in multicore and multi-threaded design requires optimized integration of hardware and software to address increasing bandwidth and power managemen

programmable multicore processors are drawing attention due to their high flexibility and low implementation cost, yet their performance and energy efficiency still cannot fulfill the demands of many compute-intensive ap

Shiqiang Zhong2, Huandong Wang2, Zichu Qi1,2, Pengyu Wang1,2, Xiang Gao2, Xu Yang2, Bin Xiao1,2, Hongsheng Wang2, Zongren Yang1,2, Liqiong Yang1,2, Shuai Chen1,2 Chinese Academy of Sciences, Beijing, China, 2 Loongson Te

in the standard place and route section. This allows for late changes to the RAMs without affecting the entire core and allows for easier process portability. AMD, Austin, TX “Jaguar” (JG) is the codename for AMD’s follo

Public-key cryptosystems (Fig. 3.3.1) have been widely developed for ensuring the security of information exchange in network communications, financial markets, private data storage, and personal identification devices.

Dawei Huang, Changku Hwang, Daisy Jian, Tim Johnson, Georgios Konstadinidis, Lance Kwong, Robert Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullois, Zuxu Qin, King Yen Oracl

Ruchir Puri4, Sean Carey2, Gerard Salem5, Guenter Mayer3, Yiu-Hing Chan2, Mark Mayo2, Adam Jatkowski2, Gerald Strevig6, Leon Sigal4, Ayan Datta7, Anne Gattiker8, Aditya Bansal4, Douglas Malone2, Thomas Strach3, Huajun We

including CPU, graphics, I/O interface, wireless transceivers and the power management unit, operate at different frequencies as shown in Fig. 3.8.1. In addition, maximizing battery life requires localized dynamic voltag

Ann Arbor, MI 1 2 AMD’s 4+ GHz x86-64 core codenamed “Piledriver” employs resonant clocking [1-4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust

Praveen Salihundam1, Shiva Ramani1, Sriram Muthukumar1, Srinivasan M1, Arun Kumar1, Shasi Kumar Gb1, Rajaraman Ramanarayanan1, Vasantha Erraguntla1, Jason Howard2, Sriram Vangal2, Saurabh Dighe2, Greg Ruhl2, Paolo Aseron

simple programming model. Recently, however, the message-passing mechanism is also drawing attention due to its potentially better scalability [1-2]. In this work, we demonstrate that a hybrid communication mechanism sup

Rahul Limaye3, Jon Duster1, Yulin Tan1, Ajay Balankutty1, Erkan Alpman1, Chun Lee1, Satoshi Suzuki1, Brent Carlton1, Hyung Seok Kim1, Marian Verhelst1, Stefano Pellerano1, Tong Kim2, Durgesh Srivastava1, Satish Venkatesa

Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert Masleid, Georgios Konstadinidis, Robert Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister Oracle, Santa Clara, CA The T4

Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, D

processor codenamed Ivy Bridge that integrates up to four high-performance Intel Architecture (IA) cores, a power/performance optimized graphics/media processing unit (GPU), as well as memory, PCIe, and display controlle

Shanghai Jiao Tong University, Shanghai, China 1 2 8K×4K Super Hi-Vision (SHV) offers a significantly enhanced visual experience relative to 1080p, and is on its way to being the next digital TV standard. In addition, ad

popular recently in a variety of industries such as automotive, surveillance, and others. SoCs for such image recognition applications are required to be powerful enough to support real-time multiple object recognition,

unmanned aerial vehicles (UAVs) and mobile augmented reality that require robust and fast recognition in the presence of dynamic camera noise. Devices in such applications suffer from severe motion/camera blur noise in l