技术领域

Digital Processors

268 篇相关论文 (2008–2026)

ISSCC 2012 Session 12 Digital Processors
A Full 4-Channel 6.3Gb/s 60GHz Direct-Conversion Transceiver with Low-Power Analog and Digital Baseband Circuitry
Kenichi Okada1, Keitarou Kondou2, Masaya Miyahara1,
Masashi Shinagawa2, Hiroki Asada1, Ryo Minami1, Tatsuya Yamaguchi1, Ahmed Musa1, Yuuki Tsukui1, Yasuo Asakura2, Shinya Tamonoki2, Hiroyuki Yamagishi2, Yasufumi Hino2, Takahiro Sato1, Hironori Sakaguchi1, Naoki Shimasaki1
ISSCC 2012 Session 12 Digital Processors
A 335Mb/s 3.9mm2 65nm CMOS Flexible MIMO Detection-Decoding Engine Achieving 4G Wireless Data Rates
Markus Winter1, Steffen Kunze1, Esther Perez Adeva1, Björn Mennenga1,
Emil Matûs1, Gerhard Fettweis1, Holger Eisenreich1, Georg Ellguth1, Sebastian Höppner1, Stefan Scholze1, René Schüffny1, Tomoyoshi Kobori2 Technical University Dresden, Dresden, Germany NEC, Tokyo, Japan 1 2 In current a
ISSCC 2012 Session 12 Digital Processors
A 32nm High-k Metal Gate Application Processor with GHz Multi-Core CPU
Se-Hyun Yang, Seogjun Lee, Jae Young Lee, Jeonglae Cho, Hoi-Jin Lee,
Dongsik Cho, Junghun Heo, Sunghoon Cho, Youngmin Shin, Sunghee Yun, Euiseok Kim, Ukrae Cho, Edward Pyo, Man Hyuk Park, Jae Cheol Son, Chinhyun Kim, Jeongnam Youn, Youngki Chung, Sungho Park, Seung Ho Hwang Samsung Electr
ISSCC 2011 Session 7 Digital Processors
A Direct Digital Frequency Synthesizer with Minimized Tuning Latency of 12ns
Alan Willson, Mukund Ojha, Shilpa Agarwal, Thriven Lai, Tzu-chieh Kuo
A downside for all direct digital synthesizer (DDS) architectures is that every DDS has a phase accumulator (PA) whose normalized phase value φ must be updated for each (sin 2πφ, cos 2πφ) output-pair produced, and such u
University of California, Los Angeles, CA
ISSCC 2011 Session 7 Digital Processors
A 70Mb/s -100.5dBm Sensitivity 65nm LP MIMO Chipset for WiMAX Portable Router
Jyh-Shin Pan, Ming-Yang Chao, Eric Yeh, Wen-Wei Yang,
Ching-Wen Hsueh, Shyuan Liao, Jian-Bang Lin, Shun-An Yang, Chin-Tai Liu, Tsai-Pao Lee, Jin-Ru Chen, Chia-Hua Chou, Min Chen, Den-Kai Juang, Jen-Hao Yeh, Chieh-Wei Liao, Po-Hung Chen, Kaipon Kao, Chia-Hsin Wu, Wen-Tso Hua
ISSCC 2011 Session 7 Digital Processors
A MIMO WiMAX SoC in 90nm CMOS for 300km/h Mobility
Gene C.H. Chuang1, Pang-An Ting1, Jen-Yuan Hsu1, Jiun-You Lai1,
standard for broadband wireless access, known as Worldwide Interoperability for Microwave Access (WiMAX), provides high throughput over long-range transmission. The key developments in the physical (PHY) layer include Or
Shun-Chang Lo1, Ying-Chuan Hsiao1, Tzi-Dar Chiueh2 1 ITRI, Hsinchu, Ta
ISSCC 2011 Session 7 Digital Processors
A 28nm 0.6V Low-Power DSP for Mobile Applications
Gordon Gammie1, Nathan Ickes2, Mahmut E Sinangil2, Rahul Rithe2,
J. Gu3, Alice Wang1, Hugh Mair1, Satyendra Datla1, Bing Rong1, Sushma Honnavara-Prasad1, Lam Ho1, Greg Baldwin1, Dennis Buss1, Anantha P Chandrakasan2, Uming Ko1 1 Texas Instruments, Dallas, TX, Massachusetts Institute o
ISSCC 2011 Session 7 Digital Processors
A 57mW Embedded Mixed-Mode Neuro-Fuzzy Accelerator for Intelligent Multi-core Processor
Jinwook Oh, Junyoung Park, Gyeonghoon Kim, Seungjin Lee, Hoi-Jun Yoo
portable game consoles, and robots for such intelligent applications as object detection, recognition, and human-computer interfaces (HCI). Most of these functions are realized in software with neural networks (NN) and f
KAIST, Daejeon, Korea Artificial intelligence (AI) functions are becom
ISSCC 2011 Session 7 Digital Processors
A 275mW Heterogeneous Multimedia Processor for IC-Stacking on Si-Interposer
Hyo-Eun Kim, Jae-Sung Yoon, Kyu-Dong Hwang, Young-Jun Kim,
processing, vision, and 3D graphics require high external memory bandwidth. In augmented-reality (AR) processors [1], both 3D graphics and vision operations are required, so memory bandwidth becomes even more critical. I
Jun-Seok Park, Lee-Sup Kim KAIST, Daejeon, Korea Most data-intensive o
ISSCC 2011 Session 7 Digital Processors
A Highly Parallel and Scalable CABAC Decoder for Next Generation Video Coding
Vivienne Sze, Anantha P. Chandrakasan
Future video decoders will need to support high resolutions such as Quad Full HD (QFHD, 4096×2160) and fast frame rates (e.g. 120fps). Many of these decoders will also reside in portable devices. The next-generation stan
Massachusetts Institute of Technology, Cambridge, MA
ISSCC 2011 Session 7 Digital Processors
A 216fps 4096×2160p 3DTV Set-Top Box SoC for Free-Viewpoint 3DTV Applications
Pei-Kuei Tsung, Ping-Chih Lin, Kuan-Yu Chen, Tzu-Der Chuang,
Hsin-Jung Yang, Shao-Yi Chien, Li-Fu Ding, Wei-Yin Chen, Chih-Chi Cheng, Tung-Chien Chen, Liang-Gee Chen National Taiwan University, Taipei, Taiwan 3DTV promises to become the mainstream of next-generation TV systems. Hi
ISSCC 2011 Session 4 Digital Processors
A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium® Processor for Mission-Critical Servers
Reid J. Riedlinger1, Rohit Bhatia1, Larry Biro2, Bill Bowhill2, Eric Fetzer1,
named Poulson, has eight multi-threaded 64 bit cores. Poulson is socket compatible with the current Intel® Itanium® Processor 9300 series (Tukwila) [1]. The new design integrates a ring-based system interface derived fro
Paul Gronowski2, Tom Grutkowski1 1 Intel, Fort Collins, CO, Intel, Hud
ISSCC 2011 Session 4 Digital Processors
Clock Generation for a 32nm Server Processor with Scalable Cores
Shenggao Li, Ashwin Krishnakumar, Edward Helder, Roan Nicholson, Vivian Jia
Intel, Santa Clara, CA Within a given power envelope, the performance of a multi-core enterprise processor is greatly affected by inter-core (including I/O) data throughput and data transport latency. This paper presents
ISSCC 2011 Session 4 Digital Processors
40-Entry Unified Out-of-Order Scheduler and Integer Execution Unit for the AMD Bulldozer x86-64 Core
Michael Golden, Srikanth Arekapudi, James Vinh
AMD’s two-core Bulldozer module [1,2] implements the AMD x86-64 microarchitecture in an 11-layer 32-nm SOI HKMG technology. The 40-instruction outof-order unified integer scheduler issues up to four operations per cycle
AMD, Sunnyvale, CA
ISSCC 2011 Session 4 Digital Processors
Design Solutions for the Bulldozer 32nm SOI 2-Core Processor Module in an 8-Core CPU
Tim Fischer1, Srikanth Arekapudi2, Eric Busta1, Carl Dietz3,
Michael Golden2, Scott Hilker2, Aaron Horiuchi1, Kevin A. Hurd1, Dave Johnson1, Hugh McIntyre2, Samuel Naffziger1, James Vinh2, Jonathan White4, Kathryn Wilcox4 instead of a traditional mismatch CAM. The integer datapath
ISSCC 2011 Session 4 Digital Processors
Godson-3B: A 1GHz 40W 8-Core 128GFLOPS Processor in 65nm CMOS
Weiwu Hu1,2, Ru Wang1,2, Yunji Chen1,2, Baoxia Fan1,2, Shiqiang Zhong1,2,
processor series, the Godson-3B processor is an 8-core high-performance general-purpose processor implemented in 65nm CMOS low-power general-purpose mixed process with 7 layers of Cu metallization. Godson-3B contains 582
Xiang Gao2, Zichu Qi1,2, Xu Yang2 1 Chinese Academy of Sciences, Beiji
ISSCC 2011 Session 4 Digital Processors
A 32nm Westmere-EX Xeon® Enterprise Processor
Shankar Sawant, Utpal Desai, Gururaj Shamanna, Lokesh Sharma,
of 10 Westmere 32nm cores [2] and a shared inclusive L3 cache (LLC) integrated on a monolithic die, with link-based I/Os. This paper focuses on the innovations and circuit optimizations over the predecessor [3] targeting
Mandar Ranade, Anil Agarwal, Sampath Dakshinamurthy, Rajagopal Narayan
ISSCC 2011 Session 4 Digital Processors
Dynamic Hit Logic with Embedded 8Kb SRAM in 45nm SOI for the zEnterpriseTM Processor
Antonio R Pelella, Yuen H Chan, Bargav Balakrishnan, Pradip Patel,
logic functions are making their way onto critical path SRAMs in the L1 cache look up structure. Described in this paper is a 14 bit dynamic hit logic scheme with an embedded 8K bit SRAM in IBM’s 45nm SOI [3]. The hit lo
Daniel Rodko, Richard E Serton IBM Systems and Technology Group, Pough
ISSCC 2011 Session 4 Digital Processors
A 5.2GHz Microprocessor Chip for the IBM zEnterpriseTM System
J. Warnock1, Y. Chan2, W. Huott2, S. Carey2, M. Fee2, H. Wen3,
M.J. Saccamango2, F. Malgioglio2, P. Meaney2, D. Plass2, Y.-H. Chan2, M. Mayo2, G. Mayer4, L. Sigal5, D. Rude2, R. Averill2, M. Wood2, T. Strach4, H. Smith2, B. Curran2, E. Schwarz2, L. Eisen3, D. Malone2, S. Weitzel3, P
ISSCC 2011 Session 15 Digital Processors
A Side-Channel and Fault-Attack Resistant AES Circuit Working on Duplicated Complemented Values
Marion Doulcier-Verdier1,2, Jean-Max Dutertre2, Jacques Fournier1,2,
Cryptographic circuits can be subjected to several kinds of side-channel and fault attacks in order to extract the secret key. Side-channel attacks can be carried by measuring either the power consumed or the EM waves em
Jean-Baptiste Rigaud2, Bruno Robisson1,2, Assia Tria1,2 1 2 CEA-LETI-M
ISSCC 2011 Session 15 Digital Processors
A Programmable Adaptive Phase-Shifting PLL for Clock Data Compensation Under Resonant Supply Noise
Dong Jiao, Chris H. Kim
Power supply noise has become one of the main performance-limiting factors in sub-1V technologies. Resonant supply noise caused by the package/bonding inductance and on-die capacitance has been reported as the dominant s
University of Minnesota, Minneapolis, MN
ISSCC 2011 Session 15 Digital Processors
A Low-Power Integrated x86-64 and Graphics Processor for Mobile Computing Devices
Srinivasa Rao Gutta1, Denis Foley2, Ajay Naini1, Robert Wasmuth3, Don Cherepacha4
AMD, Hyderabad, India, AMD, Boxborough, MA, 3 AMD, Austin, TX, 4 AMD, Markham, Canada 2 AMD’s first Fusion Accelerated Processor Unit (APU) codenamed “Zacate” (Fig. 15.4.1) combines a pair of x86 CPUs cores codenamed “Bo
ISSCC 2011 Session 15 Digital Processors
A Fully-Integrated 3-Level DC/DC Converter for Nanosecond-Scale DVS with Fast Shunt Regulation
Wonyoung Kim, David M Brooks, Gu-Yeon Wei
In recent years, chip multiprocessor architectures have emerged to scale performance while staying within tight power constraints. This trend motivates percore/block dynamic voltage and frequency scaling (DVFS) with fast
Harvard University, Cambridge, MA
ISSCC 2011 Session 15 Digital Processors
An 80Gb/s Dependable Communication SoC with PCI Express I/F and 8 CPUs ports realizes a high performance communication link with a theoretical peak bandwidth of 4×20Gb/s.
Sugako Otani1, Hiroyuki Kondo1, Itaru Nonomura2, Atsuyuki Ikeya2,
Minoru Uemura2, Yasushi Hayakawa1, Takeshi Oshita1, Satoshi Kaneko1, Katsushi Asahina2, Kazutami Arimoto1, Shin’ichi Miura3, Toshihiro Hanawa3, Taisuke Boku3, Mitsuhisa Sato3 Figure 15.2.4 shows the PCIe PHY analog block
ISSCC 2010 Session 5 Digital Processors
A 4.1Tb/s Bisection-Bandwidth 560Gb/s/W Streaming Circuit-Switched 8×8 Mesh Network-on-Chip in 45nm CMOS
Mark A Anders, Himanshu Kaul, Steven K Hsu, Amit Agarwal,
core-to-core communication, are key to enabling future tera-scale multi-core processors. Packetswitched 2D mesh networks provide efficient interconnect utilization, low latencies and high throughputs, but suffer from low
Sanu K Mathew, Farhana Sheikh, Ram K Krishnamurthy, Shekhar Borkar Int
ISSCC 2010 Session 5 Digital Processors
A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS
Jason Howard1, Saurabh Dighe1, Yatin Hoskote1, Sriram Vangal1,
David Finan1, Gregory Ruhl1, David Jenkins1, Howard Wilson1, Nitin Borkar1, Gerhard Schrom1, Fabrice Pailet1, Shailendra Jain2, Tiju Jacob2, Satish Yada2, Sraven Marella2, Praveen Salihundam2, Vasantha Erraguntla2, Micha
ISSCC 2010 Session 5 Digital Processors
An x86-64 Core Implemented in 32nm SOI CMOS
Ravi Jotwani1, Sriram Sundaram1, Stephen Kosonocky2, Alex Schaefer1,
occupies 9.69mm2, contains more than 35 million transistors (excluding L2 cache), and operates at frequencies in excess of 3GHz. The core incorporates numerous design and power improvements to enable an operating range o
Victor Andrade1, Greg Constant1, Amy Novak1, Samuel Naffziger2 1 AMD,
ISSCC 2010 Session 5 Digital Processors
A Wire-Speed PowerTM Processor: 2.3GHz 45nm SOI with 16 Cores and 64 Threads
Charles Johnson1, David H. Allen2, Jeff Brown2, Steve Vanderwiel2,
Russ Hoover2, Heather Achilles3, Chen-Yong Cher4, George A. May5, Hubertus Franke4, Jimi Xenedis4, Claude Basso6 1 IBM Research, Rochester, MN IBM Systems and Technology Group, Rochester, MN 3 IBM Research, Bedford, NH 4
ISSCC 2010 Session 5 Digital Processors
The Implementation of POWER7TM: A Highly Parallel and Scalable Multi-Core High-End Server Processor
Dieter Wendel1, Ronald Kalla2, Robert Cargoni2, Joachim Clables2,
Joshua Friedrich2, Roland Frech1, James Kahle2, Balaram Sinharoy3, William Starke2, Scott Taylor2, Steve Weitzel2, Sam G. Chu2, Saiful Islam2, Victor Zyuban4 1 IBM, Boeblingen, Germany IBM, Austin, TX 3 IBM, Poughkeepsie
ISSCC 2010 Session 5 Digital Processors
A 45nm 37.3GOPS/W Heterogeneous Multi-Core SoC
Yoichi Yuyama1, Masayuki Ito1, Yoshikazu Kiyoshige1, Yusuke Nitta1,
Shigezumi Matsui1, Osamu Nishii1, Atsushi Hasegawa1, Makoto Ishikawa2, Tetsuya Yamada2, Junichi Miyakoshi2, Koichi Terada2, Tohru Nojiri2, Makoto Satoh2, Hiroyuki Mizuno2, Kunio Uchiyama2, Yasutaka Wada3, Keiji Kimura3,
ISSCC 2010 Session 5 Digital Processors
A 40nm 16-Core 128-Thread CMT SPARC SoC Processor
Jinuk Luke Shin, Kenway Tam, Dawei Huang, Bruce Petrick, Ha Pham,
Changku Hwang, Hongping Li, Alan Smith, Timothy Johnson, Francis Schumacher, David Greenhill, Ana Sonia Leon, Allan Strong Sun Microsystems, Santa Clara, CA This next generation of Chip Multithreaded (CMT) SPARC SoC proc
ISSCC 2010 Session 5 Digital Processors
Westmere: A Family of 32nm IA Processors
Nasser A. Kurd, Subramani Bhamidipati, Christopher Mozak,
Jeffrey L. Miller, Timothy M. Wilson, Mahadev Nemani, Muntaquim Chowdhury Intel, Hillsboro, OR The Westmere processor is implemented on a high-κ metal-gate 32nm process technology [1] as a compaction of the Nehalem proce
ISSCC 2010 Session 15 Digital Processors
Millimeter-Scale Nearly Perpetual Sensor System with Stacked Battery and Solar Cells
Gregory Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park,
in medical, infrastructure and environmental monitoring. Due to volume constraints, sensor systems are often capable of storing only small amounts of energy. Several systems have increased lifetime through VDD scaling [1
Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis Sylvester, David Blaau
ISSCC 2010 Session 15 Digital Processors
A 45nm CMOS 13-Port 64-Word 41b Fully Associative Content-Addressable Register File
Greg Burda, Yesh Kolla, Jim Dieffenderfer, Fadi Hamdan
The high-performance needs of mobile products has motivated CPU designers to increase processing performance while decreasing power consumption. A dual-issue out-of-order superscalar ARMv7-architecture CPU uses the techn
Qualcomm, Raleigh, NC
ISSCC 2010 Session 15 Digital Processors
A Power-Efficient 32b ARM ISA Processor Using Timing-Error Detection and Correction for TransientError Tolerance and Adaptation to PVT Variation
David Bull1, Shidhartha Das1, Karthik Shivshankar1, Ganesh Dasika2,
detection and correction of timing errors. A combination of error-detecting circuits and micro-architectural recovery mechanisms creates a system which is robust in the face of timing errors, and can be tuned to an effic
Krisztian Flautner1, David Blaauw2 1 ARM, Cambridge, United Kingdom Un
ISSCC 2010 Session 15 Digital Processors
A 45nm Resilient and Adaptive Microprocessor Core for Dynamic Variation Tolerance
James Tschanz, Keith Bowman, Shih-Lien Lu, Paolo Aseron,
Muhammad Khellah, Arijit Raychowdhury, Bibiche Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De Intel, Hillsboro, OR Microprocessors experience a wide range of dynamic variations, including voltage droo
ISSCC 2010 Session 15 Digital Processors
A 2Gb/s Network Processor with a 24mW IPsec Offload for Residential Gateways
Yukikuni Nishida, Kenji Kawai, Keiichi Koike
The Internet has become an important tool to deliver services such as Voice over Internet Protocol (IP) and high-definition video. To enable the widespread use of these services, it is essential to ensure quality-of-serv
NTT, Kanagawa, Japan
ISSCC 2010 Session 15 Digital Processors
A 477mW NoC-Based Digital Baseband for MIMO 4G SDR
Fabien Clermidy1, Christian Bernard1, Romain Lemaire1, Jerome Martin1,
processing for advanced Telecom applications have to face two contradictory issues [1]. The first one is the flexibility required, with the exploding number of modes for a single protocol (e.g. 63 for 3GPP-LTE), the numb
Ivan Miro-Panades1, Yvain Thonnart1, Pascal Vivet1, Norbert Wehn2 1 CE
ISSCC 2010 Session 15 Digital Processors
A 4.5mW Digital Baseband Receiver for Level-A Evolved EDGE
Christian Benkeser1,2, Andreas Bubenhofer1, Qiuting Huang1,2, 1
given fresh impetus to 3G technology and beyond, which provides a key enabler to the mobile industry’s only current growth sector. Despite the high data rates of 3G-enabled devices, good user experience still crucially d
ETH Zürich, Zürich, Switzerland Advanced Circuit Pursuit (ACP), Zollik
ISSCC 2010 Session 15 Digital Processors
A 390Mb/s 3.57mm2 3GPP-LTE Turbo Decoder ASIC in 0.13µm CMOS
Christoph Studer1, Christian Benkeser1,2, Sandro Belfanti1,
devices has vindicated 3G (WCDMA/HSPA) as an enabling technology for mainstream high-speed data and has given fresh impetus to its 4G successor, LTE (Long-Term Evolution). With mass deployment anticipated in 2-to-3 years
Quiting Huang1,2 1 ETH Zürich, Zürich, Switzerland Advanced Circuit Pu
ISSCC 2009 Session 8 Digital Processors
A 342mW Mobile Application Processor with Full-HD Multi-Standard Video Codec
Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu
Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori Renesas Technology, Tokyo, Japan Today’s cellular phones must
ISSCC 2009 Session 8 Digital Processors
A 45nm Single-Chip Application-and-Baseband Processor Using an Intermittent Operation Technique
Motoyasu Shirasaki, Yusaku Miyazaki, Masahiro Hoshaku,
Hiroo Yamamoto, Sachio Ogawa, Takuya Arimura, Hiroshi Hirai, Yasuo Iizuka, Tsutomu Sekibe, Yoichi Nishida, Toshiyuki Ishioka, Junji Michiyama Panasonic, Yokohama, Japan Mobile phones demand high-performance application p
ISSCC 2009 Session 8 Digital Processors
A 212MPixels/s 4096×2160p Multiview Video Encoder Chip for 3D/Quad HDTV Applications
Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Hsu-Kuang
Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien, Tung-Chien Chen, Ping-Chih Lin, Chia-Yu Chang, Liang-Gee Chen National Taiwan University, Taipei, Taiwan To provide more vivid perception, TV resolution is increasing dra
ISSCC 2009 Session 8 Digital Processors
A Multi-Format Blu-ray Player SoC in 90nm CMOS
Chi-Cheng Ju, Tsu-Ming Liu, Chih-Chieh Yang, Shih-Hung Lin, Kuo-Pin
Lan, Chien-Hua Wu, Ting-Hsun Wei, Chi-Chin Lien, Jiun-Yuan Wu, Chih-Hao Hsiao, Te-Wei Chen, Yeh-Lin Chu, Guan-Yi Lin, Yung-Chang Chang, Kung-Sheng Lin, Chih-Ming Wang, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Chien-H
ISSCC 2009 Session 8 Digital Processors
A 201.4GOPS 496mW Real-Time Multi-Object Recognition Processor with Bio-Inspired Neural Perception Engine
Joo-Young Kim, Minsu Kim, Seungjin Lee, Jinwook Oh, Kwanho Kim,
recognition [1], was applied to the implementation of a high performance object recognition chip [2]. Even though the previous chip achieved 50% gain of computational cost [2], it could recognize only one object in a fra
Sejong Oh, Jeong-Ho Woo, Donghyun Kim, Hoi-Jun Yoo KAIST, Daejeon, Kor
ISSCC 2009 Session 8 Digital Processors
A Versatile Recognition Processor Employing HaarLike Feature and Cascaded Classifier
Yuya Hanai, Yuichi Hori, Jun Nishimura, Tadahiro Kuroda
This paper presents a versatile recognition processor that performs detection and recognition of image, video, sound and acceleration signals, while dissipating 0.15µW/fps to 0.47mW/fps (Fig. 8.2.1). Given the low power
Keio University, Yokohama, Japan
ISSCC 2009 Session 8 Digital Processors
An Ultra-Low-Energy/Frame Multi-Standard JPEG CoProcessor in 65nm CMOS with Sub/Near-Threshold Power Supply
Yu Pu1,2,3, Jose Pineda de Gyvez1,2, Henk Corporaal1, Yajun Ha3
NXP Semiconductors, Eindhoven, Netherlands 3 National University of Singapore, Singapore power switch transistors S0, S1 and S2 are designed with NMOS transistors with their gate control voltage boosted to 1.2V, which is
Eindhoven University of Technology, Netherlands
ISSCC 2009 Session 3 Digital Processors
Over One Million TPCC with a 45nm 6-Core Xeon® CPU This paper describes the 6-core Xeon® 7400 series processor family, codename Dunnington, designed for a broad range of highly power efficient servers. The processor consists of three dual-core 45nm CoreTM processors [1] and a shared inclusive 16MB L3 cache (LLC) integrated on a monolithic 503mm2 die. The system interface is FSB based with the I/Os incorporated into the center of the die. Figure 3.8.1 shows the chip floorplan. The core-to-FSB connection is replaced with an on-die low-latency uncore interface. The uncore arbitrates among core, LLC, and external bus requests. The processor has 1.9B transistors and is implemented in 45nm CMOS using high-κ metalgate transistors and nine copper interconnect layers [2]. The maximum thermal design power is 130W. There are 8 PLLs on a single die with a cascaded pair serving its respective
core or uncore, as shown in Fig. 3.8.4. PLLs are fed from a single external bus, clock (xxCLK: 266MHz) C4-bump pair with
high-frequency clock (GCLK) supporting the core; and a half- frequency clock that supports most of the uncore logic and the LLC. In the cascaded configuration, the I/O PLL receives the xxCLK and synthesizes the 4× freque
ISSCC 2009 Session 3 Digital Processors
Dual-DLL-Based CMOS All-Digital Temperature Sensor for Microprocessor Thermal Monitoring
Kyoungho Woo1, Scott Meninger2, Thucydides Xanthopoulos2,
increasingly need on-chip temperature sensors for thermal and power management [1]. Since these sensors do not take part in the main computing activity but rather play the auxiliary, albeit important, role of temperature
Ethan Crain2, Dongwan Ha1, Donhee Ham1 1 Harvard University, Cambridge
ISSCC 2009 Session 3 Digital Processors
A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS
Byungsub Kim, Vladimir Stojanovic
This paper presents a transceiver for fast and energy-efficient global on-chip communication, consisting of a nonlinear charge-injecting (CI) 3-tap transmit filter (TX) and a sampling receiver (RX) with transimpedance pr
Massachusetts Institute of Technology, Cambridge MA