An Ultra-Low-Energy/Frame Multi-Standard JPEG CoProcessor in 65nm CMOS with Sub/Near-Threshold Power Supply

📋 论文概要

该论文提出了一种在65nm CMOS工艺中采用亚/近阈值供电的多标准JPEG协处理器，实现了超低每帧能耗。通过使用可配置VT平衡器和升压电源开关晶体管，解决了亚阈值操作下工艺变化导致的时序不确定性问题。

💡 主要创新点

• 采用可配置VT平衡器，在0.4V供电下将关键路径的时序标准差降低4.7倍，σ/μ降低3.6倍。
• 使用NMOS电源开关晶体管，其栅极控制电压升压至1.2V（I/O电压），增强了驱动能力。
• 实现了多标准JPEG协处理器的亚/近阈值操作，显著降低每帧能耗。

🏷 关键词

📄 原文摘要

NXP Semiconductors, Eindhoven, Netherlands 3 National University of Singapore, Singapore power switch transistors S0, S1 and S2 are designed with NMOS transistors with their gate control voltage boosted to 1.2V, which is the VDDIO for pads, so the driving capability is increased. The Monte-Carlo transient time simulation for a critical path at VDD=0.4V shows that the standard deviation σ is reduced by 4.7× and the σ/µ is reduced by 3.6× when the configurable VT balancer is used. 1 2 Many digital ICs can benefit from sub/near threshold operations that provide ultra-low-energy/operation for long battery lifetime. In addition, sub/near threshold operation largely mitigates the transient current hence lowering the ground bounce noise. This also helps to improve the performance of sensitive analog circuits on the chip, such as delay-lock loops (DLL), which is crucial for the functioning of large digital circuits. However, aggressive voltage scaling causes throughput and reliability degradat

👥 作者与机构

Yu Pu1,2,3, Jose Pineda de Gyvez1,2, Henk Corporaal1, Yajun Ha3

Eindhoven University of Technology, Netherlands