技术领域

Digital Processors

268 篇相关论文 (2008–2026)

ISSCC 2009 Session 3 Digital Processors
Secure AES Engine with A Local Switched-Capacitor Current Equalizer
Carlos Tokunaga, David Blaauw
Hardware implementations of the popular AES encryption algorithm [1,2] provide attackers with important side-channel information (delay, power consumption or EM radiation) that can be used to disclose the secret key of t
University of Michigan, Ann Arbor, MI
ISSCC 2009 Session 3 Digital Processors
Dynamic Frequency-Switching Clock System on A Quad-Core Itanium® Processor
Andrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger
Intel, Fort Collins, CO The 700mm2 65nm Itanium® processor codenamed Tukwila [1] integrates four cores and a system interface with six QuickPath® interconnect channels and four memory interconnect channels. The large die
ISSCC 2009 Session 3 Digital Processors
A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors
Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada,
number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide ba
Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi,
ISSCC 2009 Session 3 Digital Processors
A Family of 45nm IA Processors
Rajesh Kumar, Glenn Hinton
Nehalem is a family of next-generation IA processors for mobile, desktop and server segments implemented in 45nm high-κ metal-gate CMOS [1]. The family features a new system architecture, significantly enhanced Core arch
Intel, Hillsboro, OR
ISSCC 2009 Session 3 Digital Processors
A 45nm 8-Core Enterprise Xeon® Processor
Stefan Rusu, Simon Tam, Harry Muljono, Jason Stinson, David Ayers,
of eight dualthreaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. Figure 3.1.1 shows the processor block diagram. This de
Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli Intel, Sant
ISSCC 2008 Session 4 Digital Processors
Circuit Design for Voltage Scaling and SER Immunity on a Quad-Core Itanium® Processor
Dan Krueger1, Erin Francom1, Jack Langsdorf2, 1
cores over its predecessor [2], from 2 to 4. It also adds a system interface that is roughly as large as two cores, including six QuickPath interconnects and four FBDIMM channels. This 3× increase in logic circuits per s
Intel, Fort Collins, CO Intel, Hudson, MA 2 The 700mm2 65nm Itanium® p
ISSCC 2008 Session 4 Digital Processors
A 65nm 2-Billion-Transistor Quad-Core Itanium® Processor
Blaine Stackhouse1, Brian Cherkauer1, Mike Gowan,
The processor has 4 dual-threaded cores integrated on die with a system interface and 30MB of cache in an 8M 65nm process. The 21.5×32.5mm2 die contains 2.05 billion transistors (Fig. 4.6.1). The silicon is designed to o
Paul Gronowski2, Chris Lyles1 1 Intel, Fort Collins, CO, 2Intel, Hudso
ISSCC 2008 Session 4 Digital Processors
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler
Masayuki Ito1, Toshihiro Hattori1, Yutaka Yoshida1, Kiyoshi Hayase1,
Tomoichi Hayashi1, Osamu Nishii1, Yoshihiko Yasu1, Atsushi Hasegawa1, Masashi Takada2, Masaki Ito2, Hiroyuki Mizuno2, Kunio Uchiyama2, Toshihiko Odaka2, Jun Shirako3, Masayoshi Mase3, Keiji Kimura3, Hironori Kasahara3 1
ISSCC 2008 Session 4 Digital Processors
TILE64TM Processor: A 64-Core SoC with Mesh Interconnect
Shane Bell, Bruce Edwards, John Amann, Rich Conlin, Kevin Joyce,
Vince Leung, John MacKay, Mike Reif, Liewei Bao, John Brown, Matthew Mattina, Chyi-Chang Miao, Carl Ramey, David Wentzlaff, Walker Anderson, Ethan Berger, Nat Fairbanks, Durlov Khan, Froilan Montenegro, Jay Stickney, Joh
ISSCC 2008 Session 4 Digital Processors
Migration of Cell Broadband EngineTM from 65nm SOI to 45nm SOI
O. Takahashi1, C. Adams2, D. Ault1, E. Behnen1, O. Chiang1,
S. R. Cottier1, P. Coulman1, J. Culp3, G. Gervais1, M. S. Gray4, Y. Itaka5, C. J. Johnson2, F. Kono5, L. Maurice1, K. W. McCullen4, L. Nguyen1, Y. Nishino6, H. Noro5, J. Pille7, M. Riley1, M. Shen1, C. Takano6, S. Tokito
ISSCC 2008 Session 4 Digital Processors
Implementation of a Third-Generation 16-Core 32Thread Chip-Multithreading SPARC® Processor
Georgios Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro,
Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar Sun Microsystems, Santa Clara, CA This third-generation chip-multithreadin
ISSCC 2008 Session 4 Digital Processors
A Third-Generation 65nm 16-Core 32-Thread Plus 32-Scout-Thread CMT SPARC® Processor
Marc Tremblay, Shailender Chaudhry
Sun Microsystems, Santa Clara, CA The goals for this high-end commercial microprocessor are high throughput and high single-thread performance, mainframe-class reliability, hardware transactional memory, and linear scala
ISSCC 2008 Session 13 Digital Processors
An 11mm2 70mW Fully-Programmable Baseband Processor for Mobile WiMAX and DVB-T/H in 0.12µm CMOS
Anders Nilsson, Eric Tell, Dake Liu
Rapid evolution of wireless standards and the increasing demand for multi-standard products make traditional fixed-function hardware for baseband processing too rigid. Programmable solutions are needed. At the same time,
Linköping University, Linköping, Sweden
ISSCC 2008 Session 13 Digital Processors
A 58mW 1.2mm² HSDPA Turbo Decoder ASIC in 0.13µm CMOS
Christian Benkeser1, Andreas Burg1, Teo Cupaiuolo1, Qiuting Huang1,2, 1
provide a compelling user experience has made HSPA an indispensable catalyst for a substantial subscriber transition from 2G to 3G [1]. Data rates reaching the full potential of 3GPP R6 from cost-effective mobile termina
ETH Zurich, Zurich, Switzerland Advanced Circuit Pursuit (ACP), Zollik
ISSCC 2008 Session 13 Digital Processors
A 9.7mW AAC-Decoding, 620mW H.264 720p
60fps Decoding, 8-Core Media Processor with
Shuou Nomura1, Fumihiko Tachibana1, Tetsuya Fujita1, Chen Kong Teh1, Hiroyuki Usui1, Fumiyuki Yamane1, Yukimasa Miyamoto1, Chaiyasit Kumtornkittikul1, Hiroyuki Hara1, Takahiro Yamashita1, Jun Tanabe1, Masato Uchiyama1, Y
Embedded Forward-Body-Biasing and PowerGating Circuit in 65nm CMOS Tec
ISSCC 2008 Session 13 Digital Processors
A 65nm Single-Chip Application and Dual-Mode Baseband Processor with Partial Clock Activation and IP-MMU 1 1 1 1
Masao Naruse , Tatsuya Kamei , Toshihiro Hattori , Takahiro Irita ,
Kenichi Nitta1, Takao Koike1, Shinichi Yoshioka1, Koji Ohno1, Masahito Saigusa2, Minoru Sakata3, Yukio Kodama4, Yuji Arai5, Teruyoshi Komuro6 1 Renesas Technology, Tokyo, Japan, 2NTT DoCoMo, Tokyo, Japan Fujitsu, Kanagaw
ISSCC 2008 Session 13 Digital Processors
A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques benefits of FBB and RBB (Fig. 13.2.3). This ABB approach achieves an optimal balance of performance and power with circuit techniques alone, eliminating the need for additional LVT or HVT logic transistors.
Gordon Gammie, Alice Wang, Minh Chau, Sumanth Gururajarao,
Robert Pitts, Fabien Jumel, Stacey Engel, Philippe Royannez, Rolf Lagerquist, Hugh Mair, Jeff Vaccani, Greg Baldwin, Keerthi Heragu, Rituparna Mandal, Michael Clinton, Don Arden, Uming Ko The device has 16Mb of SRAM and
ISSCC 2008 Session 13 Digital Processors
A Sub-1W to 2W Low-Power IA Processor for Mobile Internet Devices and Ultra-Mobile PCs in 45nm Hi-κ Metal Gate CMOS
Gianfranco Gerosa, Steve Curtis, Mike D’Addeo, Bo Jiang,
specifically designed for Mobile Internet Devices (MID) and UltraMobile PCs (UMPC) where average power consumed is in the order of a few hundred mW (as measured by MobileMark’05 OP @ 60 nits brightness) with performance
Belliappa Kuttanna, Feroze Merchant, Binta Patel, Mohammed Taufique, H