A 45nm 8-Core Enterprise Xeon® Processor

📋 论文概要

该论文介绍了一款采用45nm工艺、集成8个Nehalem核心和共享L3缓存的至强处理器，解决了多核处理器在高性能计算中的功耗和系统拓扑支持问题。

💡 主要创新点

• 采用金属栅极高k介质晶体管和9层铜互连的45nm CMOS工艺，实现2.3B晶体管集成。
• L3缓存由8个切片组成，每个切片包含48个子阵列，支持24路组相联和64字节缓存行。

🏷 关键词

📄 原文摘要

of eight dualthreaded 64b Nehalem cores and a shared L3 cache. The system interface includes two on-chip memory controllers and supports multiple system topologies. Figure 3.1.1 shows the processor block diagram. This design has 2.3B transistors and is implemented in 45nm CMOS using metal-gate high-κ dielectric transistors and nine Cu interconnect layers [1]. The thermal design power is 130W. ® The L3 cache is built from eight slices, each having 2048 sets and 24 ways. Each cache line is 64 bytes constructed into 2 chunks. There are a total of 48 sub-arrays in each slice [2], as shown in Fig. 3.1.2. To reduce the L3-cacheslice active power, only 3.125% of the arrays are powered up for each access. The data array uses a 0.3816µm2 cell and is protected by inline double-errorcorrection and triple-error-detection (DECTED) ECC scheme with variable

👥 作者与机构

Stefan Rusu, Simon Tam, Harry Muljono, Jason Stinson, David Ayers,

Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli Intel, Santa Clara, CA The next-generation enterprise Xeon server processor consists