Dynamic Frequency-Switching Clock System on A Quad-Core Itanium® Processor

📋 论文概要

这篇论文介绍了一种应用于四核安腾处理器的动态频率切换时钟系统，采用级联PLL架构，旨在解决大芯片、高集成度和工艺可变性带来的功耗与可变性补偿挑战。

💡 主要创新点

• 提出动态频率切换时钟系统，通过级联PLL架构实现灵活的频率调节和功耗优化。
• 引入针对工艺可变性的补偿机制，确保在大规模集成（700mm²）下时钟信号的稳定性和可靠性。

🏷 关键词

📄 原文摘要

Intel, Fort Collins, CO The 700mm2 65nm Itanium® processor codenamed Tukwila [1] integrates four cores and a system interface with six QuickPath® interconnect channels and four memory interconnect channels. The large die, shown in Fig. 3.4.6, and high level of integration coupled with process variability present clock-system design challenges in the areas of power consumption and variability compensation that we discuss in this paper. Figure 3.4.1 shows the clock system, which is a cascaded-PLL architecture with an initial filter PLL that receives a 133MHz reference clock. This maiden PLL filters reference-clock jitter and outputs a 133MHz clock to 13 downstream PLLs. Each downstream PLL has a duty-cycle corrector that monitors and corrects the end-of-route duty cycle. The post-PLL clock distributions for the core, system interface, and memory/processor interconnect digital-logic domains follow a common architecture. A balanced-H-tree clock route provides a full-swing clock to the seco

👥 作者与机构

Andrew Allen, Jay Desai, Frank Verdico, Ferd Anderson, David Mulvihill, Dan Krueger