A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors

📋 论文概要

论文提出了一种芯片堆叠内存架构，用于片上SRAM丰富的SoC和处理器，通过垂直堆叠和共享本地存储器，解决多IP核平均利用率低导致的存储器浪费问题，提高资源利用率和能效。

💡 主要创新点

• 提出芯片堆叠内存技术，利用垂直堆叠实现高密度和高带宽存储，突破平面集成限制。
• 实现动态共享本地存储器给多个IP核，减少空闲存储器浪费，提升整体系统效率。

🏷 关键词

📄 原文摘要

number of dedicated functional IP cores, including 3D graphics and video codec, and require local memories with high bit density. Each IP core is connected to closely positioned local memories for fast access and wide bandwidth. The simultaneous operation of all of IP cores on a chip is an extremely rare situation and we anticipate that future integration of more IP cores onto a chip will increase the average number of sleeping IP cores at any given time. Therefore, current chip architectures that allocate local memories to individual IP cores will become increasingly inefficient in thier use of memory resources. In contrast to this, is the use of an off-chip external memory shared by a number of IP cores. Previous designs use a multilayer bus [1] and an MMU [2] for each IP core on

👥 作者与机构

Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada,

Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno NEC, Kanagawa, Japan Advanced SoC chips used in multimedia devices such as mobile phones have a