Over One Million TPCC with a 45nm 6-Core Xeon® CPU This paper describes the 6-core Xeon® 7400 series processor family, codename Dunnington, designed for a broad range of highly power efficient servers. The processor consists of three dual-core 45nm CoreTM processors [1] and a shared inclusive 16MB L3 cache (LLC) integrated on a monolithic 503mm2 die. The system interface is FSB based with the I/Os incorporated into the center of the die. Figure 3.8.1 shows the chip floorplan. The core-to-FSB connection is replaced with an on-die low-latency uncore interface. The uncore arbitrates among core, LLC, and external bus requests. The processor has 1.9B transistors and is implemented in 45nm CMOS using high-κ metalgate transistors and nine copper interconnect layers [2]. The maximum thermal design power is 130W. There are 8 PLLs on a single die with a cascaded pair serving its respective

📋 论文概要

该论文介绍了采用45nm工艺的6核Xeon® 7400系列处理器，实现了超过一百万TPCC的性能。通过创新的时钟分配和去偏斜方案，解决了大芯片上的时钟同步和功耗管理问题。

💡 主要创新点

• 采用级联PLL配置，从单一外部总线生成多个时钟域，支持核心和Uncore逻辑的不同频率需求。
• 每个核心具有独立的去偏斜方案，以应对大芯片上的工艺变化，确保时钟精确同步。
• 通过片上稳压器为每个PLL提供独立的后硅调整能力，优化功耗和性能。

🏷 关键词

📄 原文摘要

high-frequency clock (GCLK) supporting the core; and a half- frequency clock that supports most of the uncore logic and the LLC. In the cascaded configuration, the I/O PLL receives the xxCLK and synthesizes the 4× frequency ZCLK. The core PLL generates the high-frequency core clock required by the core logic. All the core and uncore PLLs are constrained to run at the same bus ratio. To combat large die variation, independent post-silicon controls are provided to adjust the supply derived from on-die regulators for each PLL. Each core has an independent de-skewing scheme [1] to have tight control on the skew. The uncore network, spanning over 30mm achieves, less than 15ps of global skew for less than 3W of power at the highest product frequency. Given the large die size and points-of-divergence that are four PLLs apart, the skew at the core-uncore boundary can be large. The core-uncore communication is

👥 作者与机构

core or uncore, as shown in Fig. 3.8.4. PLLs are fed from a single external bus, clock (xxCLK: 266MHz) C4-bump pair with balanced distribution. The processor has three clock domains: quad-pumped FSB clock (ZCLK: 1067MHz);