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ISSCC 2009Session 8 · MULTIMEDIA PROCESSORSDigital Processors

A 212MPixels/s 4096×2160p Multiview Video Encoder Chip for 3D/Quad HDTV Applications

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📋 论文概要

该论文提出了一款支持4096×2160p分辨率的212MPixels/s多视点视频编码器芯片,用于3D/四倍高清电视应用。通过视差估计有效利用视间冗余,降低比特率20%-30%。

💡 主要创新点

核心指标
212MPixels/s
重要性
发表年份
ISSCC 2009

🏷 关键词

多视点视频编码视差估计H.264/AVC高清电视芯片实现

📄 原文摘要

Chiu, Yu-Han Chen, Pai-Heng Hsiao, Shao-Yi Chien, Tung-Chien Chen, Ping-Chih Lin, Chia-Yu Chang, Liang-Gee Chen National Taiwan University, Taipei, Taiwan To provide more vivid perception, TV resolution is increasing dramatically. In addition, 3D video is emerging because it can present immersive and complete scenes. Therefore, multiview video coding (MVC) is currently being developed as an extension of H.264/AVC [1]. Disparity estimation (DE), which effectively exploits the inter-view redundancy and reduces bit rates 20% to 30%, is the most significant feature. However, DE and motion estimation (ME) require ultra-high computation and memory access. To encode a 3-view 1080p video, 82.4TOPS computing power and 54.6TB/s memory access are required with a full search algorithm. Moreover, view scalability is a critical functionality to deal with various MVC structures. There are 3 challenges to design an efficient MVC encoder chip: 1) Encoding

👥 作者与机构

Li-Fu Ding, Wei-Yin Chen, Pei-Kuei Tsung, Tzu-Der Chuang, Hsu-Kuang

分类:Digital Processors · 年份:ISSCC 2009