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ISSCC 2012Session 12 · MULTIMEDIA & COMMUNICATIONS SoCsDigital Processors65nm CMOS

A 335Mb/s 3.9mm2 65nm CMOS Flexible MIMO Detection-Decoding Engine Achieving 4G Wireless Data Rates

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📋 论文概要

该论文设计了一种灵活的MIMO检测解码引擎,旨在支持WiMAX、3GPP-LTE等4G无线标准中的多种操作模式。在65nm CMOS工艺下,实现了335Mb/s的数据速率和3.9mm2的面积,解决了接收端MIMO检测与迭代前向纠错的高复杂度问题。

💡 主要创新点

核心指标
335Mb/s @ 65nm CMOS, 3.9mm²
工艺节点
65nm CMOS
重要性
发表年份
ISSCC 2012

🏷 关键词

MIMO检测前向纠错4G无线65nm CMOS基带处理

📄 原文摘要

Emil Matûs1, Gerhard Fettweis1, Holger Eisenreich1, Georg Ellguth1, Sebastian Höppner1, Stefan Scholze1, René Schüffny1, Tomoyoshi Kobori2 Technical University Dresden, Dresden, Germany NEC, Tokyo, Japan 1 2 In current and future wireless standards, such as WiMAX, 3GPP-LTE or LTEAdvanced, receiver terminals have to support numerous operating modes for each protocol [1], as well as sophisticated transmission techniques, especially enhanced MIMO detection and iterative forward error correction (FEC). MIMO detection and FEC belong to the most computationally complex parts of the receiver-side baseband signal processing chain. Implementations thereof must have low power consumption, but also be able to interact in a flexible and efficient way in the detection-decoding engine, while at the same time not compromising on the challenging throughput and flexibility requirements associated with 4G standards. In this paper, we present a chip implementation of a MIMO

👥 作者与机构

Markus Winter1, Steffen Kunze1, Esther Perez Adeva1, Björn Mennenga1,

分类:Digital Processors · 年份:ISSCC 2012