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ISSCC 2009Session 3 · MICROPROCESSOR TECHNOLOGIESDigital Processors

A 4Gb/s/ch 356fJ/b 10mm Equalized On-chip Interconnect with Nonlinear Charge-Injecting Transmit Filter and Transimpedance Receiver in 90nm CMOS

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📋 论文概要

该论文提出了一种用于全局片上通信的收发器,采用非线性电荷注入3抽头发射滤波器和带跨阻前置放大器的采样接收器,通过模式相关电流注入实现前馈均衡,在10mm互连上达到4Gb/s/ch的速率和356fJ/b的能效。

💡 主要创新点

核心指标
4Gb/s/ch, 356fJ/b, 10mm
重要性
发表年份
ISSCC 2009

🏷 关键词

片上互连电荷注入前馈均衡低功耗收发器

📄 原文摘要

This paper presents a transceiver for fast and energy-efficient global on-chip communication, consisting of a nonlinear charge-injecting (CI) 3-tap transmit filter (TX) and a sampling receiver (RX) with transimpedance pre-amplifier (TIA). Recently, pre-emphasis techniques [1-4] have demonstrated significantly better energy-efficiency than repeater interconnects. To further improve energy-efficiency over pre-emphasis techniques that require analog subtraction [3,5], our TX selects a pattern-dependent current to inject into the wire, performing feed-forward equalization (FFE) while mitigating the nonlinearity of the driver. This 3-tap charge-injecting (CI) FFE enables stronger equalization than the capacitively driven TX [1,2] or edge-detection pre-emphasis [4], achieving data-rate of 4Gb/s over a 1cm on-chip wire. The TIA at RX improves bandwidth, signal amplitude, and reduces bias power, breaking the trade-offs

👥 作者与机构

Byungsub Kim, Vladimir Stojanovic

Massachusetts Institute of Technology, Cambridge MA

分类:Digital Processors · 年份:ISSCC 2009