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ISSCC 2012Session 3 · PROCESSORSDigital Processors

An 800MHz 320mW 16-Core Processor with Message-Passing and Shared-Memory Inter-Core Communication Mechanisms

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📋 论文概要

提出一款16核处理器,采用混合通信机制同时支持消息传递和共享内存,以提升性能和能效。通过基于簇的分层架构和无缓存内存层次结构(扩展寄存器文件、小型私有存储和中等共享存储)实现高效核间通信。

💡 主要创新点

重要性
发表年份
ISSCC 2012

🏷 关键词

多核处理器消息传递共享内存混合通信簇式架构

📄 原文摘要

simple programming model. Recently, however, the message-passing mechanism is also drawing attention due to its potentially better scalability [1-2]. In this work, we demonstrate that a hybrid communication mechanism supporting both message passing and shared memory can provide both higher performance and energy efficiency. This 16-core processor has 3 key features: (1) A cluster-based hierarchical architecture supporting both shared-memory and message-passing communication. (2) A cache-free memory hierarchy with an extended register file, small private memory and moderate shared memory to avoid complex cache coherence issues and achieve high energy efficiency by keeping data accesses local. (3) A hardware-aided mailbox mechanism to accelerate the synchronization procedure between different processor nodes. With

👥 作者与机构

Zhiyi Yu, Kaidi You, Ruijin Xiao, Heng Quan, Peng Ou, Yan Ying,

Haofan Yang, Ming’e Jing, Xiaoyang Zeng Fudan University, Shanghai, China Almost all multicore processors use a shared-memory architecture due to its

分类:Digital Processors · 年份:ISSCC 2012