A Reconfigurable Distributed All-Digital Clock Generator Core With SSC and Skew Correction in 22nm High-k Tri-Gate LP CMOS

📋 论文概要

该论文提出了一种可重构的分布式全数字时钟发生器核心，支持扩频时钟和偏斜校正，在22nm高k三栅极低功耗CMOS工艺中实现。它解决了多时钟域系统中时钟生成、偏斜最小化和快速唤醒等挑战。

💡 主要创新点

• 提出分布式全数字时钟发生器架构，支持多时钟域独立生成和动态电压频率缩放。
• 集成扩频时钟和偏斜校正功能，减少电磁干扰和模块间时钟偏斜。
• 支持快速睡眠和唤醒，降低功耗并延长电池寿命。

🏷 关键词

📄 原文摘要

including CPU, graphics, I/O interface, wireless transceivers and the power management unit, operate at different frequencies as shown in Fig. 3.8.1. In addition, maximizing battery life requires localized dynamic voltage frequency scaling (DVFS) and sleep mode support leading to independent clock domains for various functional unit blocks (FUBs). Also, clock generation units should be able to go to sleep and wake up rapidly to conserve power. Generating multiple clock signals while minimizing skews at the module interfaces is challenging. Furthermore, some modules require spread spectrum clocking (SSC), with different modulation patterns to avoid EMI, but yet such spreading is forbidden in modules requiring frequency accuracy (e.g. display interfaces). Diverse SSC generation requirements necessitate multiple reference clocks, extra pins, and

👥 作者与机构

Y. William Li1, Carlos Ornelas2, Hyung Seok Kim1, Hasnain Lakdawala1,

Ashoke Ravi1, Krishnamurthy Soumyanath1 Intel, Hillsboro, OR Intel, Guadalajara, Mexico 1 2 As platform integration continues, different modules,