Resonant Clock Design for a Power-Efficient High-Volume x86-64 Microprocessor

📋 论文概要

该论文介绍了AMD“Piledriver”x86-64微处理器中采用的谐振时钟设计技术，通过两种工作模式（直接驱动和共振）实现高达24%的时钟分布功耗降低，同时保持低时钟偏移，并满足商用处理器的宽频范围测试性和鲁棒性要求。

💡 主要创新点

• 创新点1：提出一种谐振时钟分配方案，利用两层厚顶部金属、高工作频率和时钟负载密度等有利条件，显著降低时钟网络功耗。
• 创新点2：设计双模式时钟系统（直接驱动模式和共振模式），以支持从低频到高频的宽范围操作，同时保证测试性和鲁棒性。
• 创新点3：在现有时钟设计方法基础上，实现低时钟偏移目标，确保高性能处理器的高速同步。

🏷 关键词

📄 原文摘要

Ann Arbor, MI 1 2 AMD’s 4+ GHz x86-64 core codenamed “Piledriver” employs resonant clocking [1-4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk) and resonant (rclk). Leveraging favorable factors such as the availability of two thick top-level metals, high operating frequency, clock-load density, and the existing clock-design methodology [5], the rclk mode was designed to enable both reduced average power dissipation and improved peak-power-constrained performance, with minimal area impact. This work represents a volume production-enabled implementation of resonant

👥 作者与机构

Visvesh Sathe1, Srikanth Arekapudi2, Charles Ouyang2,

Marios Papaefthymiou3,4, Alexander Ishii3, Samuel Naffziger1 AMD, Fort Collins, CO AMD, Sunnyvale, CA 3 Cyclos Semiconductor, Berkeley, CA 4 University of Michigan,