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ISSCC 2012Session 3 · PROCESSORSDigital Processors

A 32-Core RISC Microprocessor with Network

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📋 论文概要

本文介绍了一款第三代多核处理器,集成了32个RISC核心,并具备网络、加速器、电源管理和可测试性等特性。该设计通过增加核心数量提升了处理性能,解决了多核处理器集成度和能效问题。

💡 主要创新点

重要性
发表年份
ISSCC 2012

🏷 关键词

多核处理器RISC集成度

📄 原文摘要

Brian Miller, Derek Brasili, Tim Kiszely, Rob Kuhn, Rahul Mehrotra, Manan Salvi, Mandar Kulkarni, Anand Varadharajan, Shi-Huang Yin, William Lin, Adam Hughes, Bill Stysiack, Vasu Kandadi, Ilan Pragaspathi, Dan Hartman, David Carlson, Vishnu Yalala, Thucydides Xanthopoulos, Scott Meninger, Ethan Crain, Mark Spaeth, Akin Aina, Suresh Balasubramanian, Joe Vulih, Pragati Tiwary, David Lin, Richard Kessler, Bruce Fishbein, Anil Jain Cavium, Marlboro, MA This paper describes our third generation multicore processor that exhibits a high level of integration [1]. The current design doubles the number of cores, triples the frequency and more than quadruples total memory bandwidth over

👥 作者与机构

Accelerators, Power Management and Testability, Features

分类:Digital Processors · 年份:ISSCC 2012