The Next-Generation 64b SPARC Core in a T4 SoC Processor

📋 论文概要

本文介绍了Oracle T4 SoC处理器中的下一代64位SPARC核心，采用双发射乱序执行架构，实现了整数性能5倍、浮点性能7倍的提升。该处理器集成了8个核心、交叉开关和统一16路4MB L3缓存，并与前代T3平台兼容。

💡 主要创新点

• 设计了新一代双发射乱序SPARC核心，大幅提升单线程性能。
• 在SoC中集成8个核心、交叉开关和统一大容量L3缓存，实现高吞吐量。
• 保持与前代T3平台兼容，便于系统升级。

🏷 关键词

📄 原文摘要

Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert Masleid, Georgios Konstadinidis, Robert Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister Oracle, Santa Clara, CA The T4 microprocessor introduces the next generation dual-issue, out-of-order SPARC core that delivers up to 5× integer and 7× floating-point single-thread performance improvement for both commercial and industry standard workloads. Eight SPARC cores, a crossbar and a unified 16-way 4MB L3 cache are implemented in the same system-on-chip platform as the predecessor T3 [1] to utilize established coherency (CLC), DDR3 (MCU), PCIE Gen2 (PEU) and 1G/10G Ethernet interfaces (NIU) (Fig. 3.3.1). Further, T4’s pin, thermal and power compatibility with the previous generation enables faster time to market for new multi-socket systems. The 403mm2 die has 855 million transistors of four different types and 12 metal layers fabricated using TSMC’s 40nm process.

👥 作者与机构

Jinuk Luke Shin, Heechoul Park, Hongping Li, Alan Smith,