⚡ 本页包含 AI 生成的分析内容，仅供参考
本文介绍了AMD下一代高性能x86-64微处理器核心“Zen 5”，采用4nm工艺制造。论文详细阐述了该核心的微架构创新，包括改进的前端、执行单元和缓存层次结构，旨在提升单线程性能、能效和安全性。解决了高性能计算中功耗、性能和面积（PPA）的权衡问题。
Carson Henrion2, Alex Schaefer1, Brett Johnson2, Sarah Bartaszewicz Tower1, Kathy Hoover1, Deepesh John1, Ted Antoniadis1, Shravan Lakshman1, Vibhor Mittal1, Brian Kasprzyk1, Ross McCoy1, Kurt Mohlman1, Anitha Mohan1, Hon-Hin Wong3, Daryl Lieu3, Russell Schreiber1, Sahilpreet Singh4, Nick Lance2, Darryl Prudich2, Justin Coppin2, Tim Jackson2, Anita Karegar2, Ryan Miller2, Sabeesh Balagangadharan5, James Pistole3, Wilson Li3, Michael McCabe3 AMD, Austin, TX AMD, Fort Collins, CO 3 AMD, Santa Clara, CA 4 AMD, Markham, Canada 5 AMD, Bangalore, India 1 2 Codenamed “Zen 5,” AMD’s next-generation, energy-efficient high-performance x86 core targets a wide array of client, server, and embedded markets. Fabricated in TSMC’s 4nm FinFET process, the 55mm2 core complex (CCX), shown in Fig. 2.1.1., contains 8.6B transistors across eight cores, each with a 1MB private L2 cache and a shared 32MB L3 cache. The “Zen 5” implementation supports configurable FP256 and FP512 data paths.
Teja Singh1, Spence Oliver1, Sundar Rangarajan1, Shane Southard1,