⚡ 本页包含 AI 生成的分析内容，仅供参考
介绍了AMD第二代7nm x86-64微处理器核心Zen3的微架构设计，实现了首次重大架构重新设计，显著提升了单线程性能和能效。通过统一L3缓存、优化前端和执行单元等改进，增强了指令级并行性和缓存效率。
Michael McCabe1, Timothy Johnson1, James Vinh1, Thomas Yiu1, Mark Wasio1, Hon-Hin Wong1, Daryl Lieu1, Jonathan White2, Benjamin Munger2, Joshua Lindner2, Javin Olson2, Steven Bakke2, Jeshuah Sniderman2, Carson Henrion3, Russell Schreiber4, Eric Busta3, Brett Johnson3, Tim Jackson3, Aron Miller3, Ryan Miller3, Matthew Pickett3, Aaron Horiuchi3, Josef Dvorak3, Sabeesh Balagangadharan 5, Sajeesh Ammikkallingal 5, Pankaj Kumar5 AMD, Santa Clara, CA AMD, Boxborough, MA 3 AMD, Fort Collins, CO 4 AMD, Austin, TX 5 AMD, Bangalore, India 1 2 “Zen 3” is the first major microarchitectural redesign in the AMD Zen family of microprocessors. Given the same 7nm process technology as the prior-generation “Zen 2” core [1], as well as the same platform infrastructure, the primary “Zen 3” design goals were to provide: 1) a significant instruction-per-cycle (IPC) uplift, 2) a substantial frequency uplift, and 3) continued improvement in power efficiency. The core complex
Thomas Burd1, Wilson Li1, James Pistole1, Srividhya Venkataraman1,