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ISSCC 2025Session 16 · HIGHLIGHTED CHIP RELEASES: DIGITAL AND MACHINE LEARNING PROCESSORSDigital Processors5nm

Tomahawk5: 51.2Tb/s 5nm Monolithic Switch Chip for AI/ML Networking

⚡ 本页包含 AI 生成的分析内容,仅供参考

📋 论文概要

本文介绍了Broadcom的Tomahawk5(TH5)单片交换芯片,采用5nm工艺实现51.2Tb/s的交换容量,是前代产品的两倍,专为下一代数据中心和AI网络设计。芯片集成了Peregrine SerDes技术,解决了高带宽、低延迟和功耗效率的关键挑战。

💡 主要创新点

核心指标
51.2Tb/s
工艺节点
5nm
重要性
发表年份
ISSCC 2025

🏷 关键词

交换芯片51.2Tb/sAI/ML网络5nm工艺SerDes

📄 原文摘要

(BCM78900 series, aka TH5) chip and the challenges of implementing a 51.2Tb/s advanced Ethernet switch in a monolithic die. We will describe several technologies that enabled TH5 realization and its advanced capabilities. TH5 is a cutting-edge switch chip designed for next-generation data center and AI networks. This chip represents a significant advancement in switch chip technology, offering 51.2Tb/s of switching capacity, which is double the bandwidth of its predecessors [1]. Integrated into the Tomahawk5 switch is Broadcom’s Peregrine SerDes technology, which represents a significant advancement in high-speed data transmission for networking applications. The integrated SerDes cores provide native support for numerous physical connectivity options, including direct attach copper (DAC), front panel

👥 作者与机构

Asad Khamisy1, Mohan Kalkunte1, Peter Del Vecchio1, Yokai Cheok1, Greg Barsky1,

Karlheinz Muth1, Reza Sharifi2 Broadcom, San Jose, CA Broadcom, Irvine, CA 1 2 This paper provides an overview of Broadcom’s Tomahawk5

分类:Digital Processors · 年份:ISSCC 2025