High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking

📋 论文概要

本文提出了一种在5nm工艺下实现的高密度、低功耗PUF设计，通过不稳定位检测和掩码技术，将误码率分别降低了23倍和39倍。采用泄漏偏置反相器结构避免了大的穿通电流，从而降低了功耗并提高了可靠性。

💡 主要创新点

• 采用泄漏偏置反相器链代替传统CMOS反相器，消除了大穿通电流，降低了功耗和可靠性问题。
• 通过不稳定位检测和掩码技术，实现了23倍和39倍的BER降低，显著提升了PUF的稳定性。
• 在5nm先进工艺节点上实现了高密度PUF设计，兼顾了低功耗和高性能。

🏷 关键词

📄 原文摘要

Nikola Nedovic1, Sanquan Song1, Brian Zimmer1, C. Thomas Gray2 Nvidia, Santa Clara, CA Nvidia, Durham, NC 1 2 causes each inverter to have a slightly different VTC and the following stages are used to amplify the voltage differences to rail-to-rail at Vout. Instead of using regular CMOS inverters, leakage-biased inverters use prevent large crowbar current flowing through the first as well as subsequent inverter stages. This avoids large power consumption and reliability concerns. However, unlike the diode-clamped inverter chain, more stages of leakage-biased inverters are required to achieve sufficient amplification before the signal can be interfaced to regular inverters. This results in slightly larger area of the PUF cell compared to the diode-clamped inverter implementation. A set of headers (not shown in Fig. 16.4.3) are included at the 128b array level and are used to enable and disable these PUF cells.

👥 作者与机构

Sudhir Shrikantha Kudva1, Mahmut Ersin Sinangil1, Stephen Tell2,