“Zen 4c”: The AMD 5nm Area-Optimized x86-64 Microprocessor Core

📋 论文概要

本文介绍了AMD在5nm工艺下设计的面积优化x86-64微处理器核心“Zen 4c”。通过减少L3缓存容量并组合L3数据宏以降低外围电路开销，实现了芯片面积仅增加10%但核心数量翻倍且总L3缓存容量保持不变。

💡 主要创新点

• 通过将L3缓存从32MB减至16MB并合并L3数据宏，显著提高了面积效率，使宏面积减少超过10%。
• 在保持总L3缓存32MB不变的前提下，将核心数量翻倍，且芯片面积仅增加10%，实现了更高的核心密度。

🏷 关键词

📄 原文摘要

3.84mm2. Side-by-side images shown in Fig. 2.2.3. To fit two CCXs onto one chiplet die, the L3 cache in one CCX was reduced from 32MB to 16MB. The extra frequency margin also allowed pairs of L3 data macros to be combined, amortizing the peripheral circuitry overhead for higher area efficiency, resulting in more than 10% macro area reduction. These two changes enabled a “Zen 4c” chiplet to have twice the number of cores and the same total amount of 32MB L3 cache, with only 10% more area than a “Zen 4” chiplet. Thomas Burd1, Srividhya Venkataraman*1, Wilson Li*1, Timothy Johnson1, Jerry Lee1, Srikirti Velaga1, Mark Wasio1, Thomas Yiu1, Franklin Bodine1, Michael McCabe1, Udin Salim1, Santosh Kumar Thouta1, Michael Golden1, Sowmya Ramachandran 1, Gokul Subramani Lakshmi Devi1, John Wuu2, Yarek Kuszczak3, Gaurav Singla3, Carson Henrion2, Andy Robison2, Sabeesh Balagangadharan4, Umesh Nair4, Naveen Srivastava4, Hari Prasad4,

👥 作者与机构

These area optimizations resulted in a “Zen 4c” core, including the L2 cache, that was, 35% smaller than the “Zen 4” core in the same process technology, 2.48mm2 versus