A 16nm 785GMACs/J 784-Core Digital Signal Processor Array

📋 论文概要

本文提出了一款基于16nm工艺的784核数字信号处理器阵列，采用多层交换盒互连和2×2 dielet组装技术（10μm间距），实现了785GMACs/J的高能效。该处理器作为粗粒度可重构阵列（CGRA），支持多程序运行时重构，在能效上接近专用加速器（2-10倍以内），解决了传统FPGA缺乏时间动态性和CGRA能效差距的问题。

💡 主要创新点

• 提出多层交换盒互连架构，实现高密度核间通信，提升可重构阵列的灵活性和效率。
• 采用2×2 dielet组装技术，通过10μm间距的微凸点实现高带宽低功耗的芯片间互连，支持大规模集成。
• 实现多程序运行时可重构能力，在保持接近专用加速器能效的同时，提供类似CPU的时间动态性。

🏷 关键词

📄 原文摘要

amount of dark silicon area in power-limited SoCs makes it attractive to consider reconfigurable architectures that could intelligently repurpose dark silicon. FPGAs are more efficient than CPUs, but lack temporal dynamics of CPUs, efficiency and throughput of accelerators. Coarse-grain reconfigurable arrays (CGRAs) can achieve higher throughput, with substantial energy efficiency gap relative to accelerators, and limited multi-program dynamics. This paper introduces a domain-specific and energyefficient (within 2-10× of accelerators) multi-program runtime-reconfigurable 784-core processor array in 16nm CMOS. Our design maximizes generality for signal processing and linear algebra with minimal area and energy penalty. The main innovation is a

👥 作者与机构

with a Multilayer Switch Box Interconnect, Assembled as a, 2×2 Dielet with 10µm-Pitch Inter-Dielet I/O for Runtime

Multi-Program Reconfiguration Uneeb Rathore*, Sumeet Singh Nagi*, Subramanian Iyer, Dejan Marković University of California, Los Angeles, CA *Equally Credited Authors (ECAs) The increasing