A 45.5fs-Integrated-Random-Jitter and -75dBc-IntegerBoundary-Spur BiCMOS Fractional-N PLL with Suppression

📋 论文概要

本文提出了一种BiCMOS分数-N PLL，通过创新的杂散抑制技术实现了45.5fs的集成随机抖动和-75dBc的整数边界杂散。该工作有效解决了分数-N PLL中因量化噪声与环路非线性相互作用导致的杂散问题，包括固定杂散和边界杂散。

💡 主要创新点

• 提出了一种新型杂散抑制方法，能够同时抑制分数杂散、整数边界杂散以及游走杂散。
• 实现了45.5fs的超低集成随机抖动，同时将整数边界杂散抑制到-75dBc以下。
• 采用BiCMOS工艺，结合模拟和数字技术优化PLL性能。

🏷 关键词

📄 原文摘要

Michael Peter Kennedy1,2, Valerio Mazzaro1,2, Stefano Tulisi3, Micheál Scully3, Niall McDermott3, James Breslin3 University College Dublin, Dublin, Ireland Microelectronic Circuits Centre Ireland, Dublin, Ireland 3 Analog Devices, Limerick, Ireland 1 2 Fractional-N PLLs are plagued by spurs that result from interaction between the shaped quantization noise introduced by the controller of the feedback divider and non-linearities in the loop. In addition to fixed spurs associated with the fractional input to the divider controller, fractional-N PLLs can also exhibit (i) fixed spurs, whose positions depend on the initial phase setting, and (ii) moving or “wandering” spurs. These become important in applications such as phased arrays that require phase offsets between multiple PLLs and radar applications where wandering spurs can be wrongly interpreted as targets. The divider controller in a fractional-N PLL is commonly implemented as a digital deltasigma modulator (DΔΣM). The principal sour

👥 作者与机构

of Fractional, Horn, and Wandering Spurs