An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM

📋 论文概要

提出了一种8.75GHz分数-N数字锁相环，采用反凸面变斜率数字时间转换器（DTC），有效消除了时间量化误差，实现了57.3fsrms的集成抖动。解决了DTC非线性和噪声导致的频谱纯度退化问题。

💡 主要创新点

• 提出反凸面变斜率DTC架构，改善了DTC的非线性和噪声，提升频谱纯度。
• 采用分数-N数字PLL结构，优路径消除参考与分频信号间的时间量化误差。

🏷 关键词

📄 原文摘要

transceivers exploit high-order modulation schemes to increase datarates and call for high-spectral-purity frequency synthesizers. To serve this purpose, a fractional-N PLL that removes the time quantization error between the reference and divider signals through a digital-to-time converter (DTC) can be used, a technique which is now widespread among high-performance PLLs (Fig. 10.1.1 top) [1]. However, nonidealities, such as the DTC non-linearity and noise, degrade spectral purity, appearing either as fractional spurs or higher in-band phase noise in the PLL spectrum. Thanks to its simplicity and superior power-jitter trade-off, a variable-slope DTC (VS-DTC) is one of the most used DTC topologies [2-5]. Unfortunately, its linearity is affected by the slopedependent propagation delay, T2, of the output sta

👥 作者与机构

Michele Rossoni*, Simone Mattia Dartizio*, Francesco Tesolin,

Giacomo Castoro, Riccardo Dell’Orto, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino Politecnico di Milano, Milan, Italy *Equally Credited Authors (ECAs) Advanced wireless