A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration lines can be reduced by ¼ compared to a conventional direct feedback DFE [1]. Furthermore, instead of using a CML buffer in the current-summing DFE, the CTLE serves as the DFE summer; hence, overall power consumption is reduced.

📋 论文概要

本文提出一款16Gb、37Gb/s的GDDR7 DRAM，采用PAM3信令，针对不同电平的码间干扰差异，提出独立应用的DFE抽头系数，并优化ZQ校准线以减少1/4的面积。

💡 主要创新点

• 针对PAM3单端信令中不同电平ISI差异，提出每个电平独立优化的DFE抽头系数
• 通过优化ZQ校准线，将校准线数量减少1/4，降低面积开销

🏷 关键词

📄 原文摘要

Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gunhee Cho, Chanyong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hong-Jun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang The amount of inter-symbol interference (ISI) is different in each signal level for singleended PAM3. Hence, the proposed DFE tap coefficient is independently applied to the upper and lower eyes via GAIN_H and GAIN_L, depending on the previous symbol. Simulation results show that, regardless of the DFE gain strength, the proposed DFE symmetrically improves the upper and lower voltage margin for the both eyes compared to a conventional PAM3 DFE [4]. Additionally, each DQ has total 8 SAs; the mismatches

👥 作者与机构

Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An,