A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer

📋 论文概要

本文提出了一款12GS/s 12位4路时间交织流水线ADC，通过全面的时间交织误差校准和线性化输入缓冲器设计，解决了高速高精度ADC中TI误差校正复杂性和输入缓冲器线性度不足的问题。

💡 主要创新点

• 提出了一种全面的TI误差背景校准方法，覆盖增益、偏移和时序误差，无需额外硬件开销。
• 设计了线性化输入缓冲器，采用补偿技术提高宽带输入下的线性度，降低功耗。

🏷 关键词

📄 原文摘要

Instituto Superior Tecnico/University of Lisboa, Lisbon, Portugal 1 2 Direct RF sampling relieves the analog front-end design and delivers high system flexibility. In >10GS/s >10b ADCs, time-interleaving (TI) is inescapable [1-3], while the number of channels and their front-end components should be minimized to achieve low power and adequate linearity for a wideband input. Moreover, the complexity and hardware cost associated with background calibrations of TI impairments should be minimized. However, prior calibrations face challenges to be comprehensive, which either confine the applicable input [1-3] or the accuracy [4,5]. This work presents a global dither-injection-facilitated comprehensive calibration of TI errors (CCTI), which features an inherent input-independent characteristic like the analog calibration of [5], but more comprehensively corrects all sources of skew. The CCTI is instantiated in a 12GS/s 12b

👥 作者与机构

Yuefeng Cao1, Minglei Zhang1, Yan Zhu1, R. P. Martins1,2, Chi-Hang Chan1

University of Macau, Macau, China