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该论文实现了一个采用16nm CMOS工艺的600Gb/s DP-QAM64相干光收发前端，包含4个105GS/s的8位ADC和DAC。通过精确建模时钟通道的传输线效应，降低了时钟抖动和歪斜，实现了高速率下的低误码率传输。
clock channel of 1.2mm. The transmission line effect of the clock channel is carefully modeled to make sure the ADC clock has low jitter and low skew with sharp rail-to-rail edges. Guansheng Li1, Adesh Garg1, Tim He1, Ullas Singh1, Jiawen Zhang1, Lakshmi Rao1, Chang Liu1, Meisam Nazari1, Yang Liu1, Yong Liu1, Heng Zhang1, Tamer Ali1,2, Hyo Gyuem Rhew1,3, Jiayoon Ru1,4, Delong Cui1, Ali Nazemi1, The transmitter consists of four 8b DACs operating at 105GS/s and one shared PLL. As Bo Zhang1, Afshin Momtaz1, Jun Cao1 shown in Fig. 18.1.3, the DAC employs a current steering structure that utilizes quarterBroadcom, Irvine, CA now with MediaTek, Irvine, CA 3 now with Samsung Electronics, Hwaseong, Korea 4 now with Peking University, Beijing, China 1 2 An ADC/DAC-based coherent optical transceiver [1] is a promising technique to boost the throughput of metro/long-haul links beyond 600Gb/s/λ. It leverages the powerful
is symmetric from PLL to the four ADCs. In order to reduce jitter and random skew, it, uses only two stages of CMOS buffers, each of which is large in size and drives a long