A 10A Computational Digital LDO Achieving 263A/mm2 Current Density with Distributed Power-Gating Switches and Time-Based Fast-Transient Controller for Mobile SoC Application in 3nm GAAFET

📋 论文概要

该论文提出一种计算型数字LDO，采用分布式电源门控开关和时间基于的控制技术，实现了10A负载电流和263A/mm^2的高电流密度，旨在简化移动SoC中PMIC-SoC电源轨并优化CPU核心功耗。

💡 主要创新点

• 使用分布式电源门控开关来减小功率FET面积，提高集成度
• 采用时间基于的控制方法实现高效率的数字LDO
• 在移动SoC中实现了高电流密度的集成LDO

🏷 关键词

📄 原文摘要

by CPU cluster to simplify the PMIC-SoC power rails in limited PCB area (VDDLIT, VDDMID and VDDBIG in Fig. 14.6.1). In order to optimize the power of each CPU core, integrated LDOs (iLDO) have recently been proposed [1-4]. However, the cost is quite high to allocate additional power-FETs and power routing, which occupy a large area in the SoC. Therefore, reducing power-FET-area is key to integrate LDOs in a mobile SoC. A previously reported LDO [1] reduced area by using bypass mode power-FETs to supply a portion of load current. However, the load current was still supplied by an analog LDO, which requires significant area. The digital LDO (DLDO) proposed in [2] needs additional power-FETs and the current delivery path could show voltage gradients from the powerFET area to the middle of the core logic area. The maximum clock frequency of a CPU

👥 作者与机构

Dongha Lee, Seki Kim, Takahiro Nomiyama, Dong-Hoon Jung, Dongsu Kim,

Jongwoo Lee, Sungung Kwak Samsung Electronics, Hwaseong, Korea In mobile SoC applications, the power rails of multicore CPUs have been merged