⚡ 本页包含 AI 生成的分析内容，仅供参考
本文提出了一款20位40MS/s的精密SAR ADC，实现了9.3nV/rtHz的低噪声和94.2dB的动态范围。针对信号链应用进行了优化，通过采样开关布局和补偿技术有效降低了时序失配问题。
Mark Vickery1, Luke Smithers1, William Buckley3, Monsoon Dutt1, Pasquale Delizia4, Derek Hummerston1, Pawel Czapor3 return high, marking the acquisition of the complementary set of 8 sampling DACs. The remaining timing mismatch is dominated by the VT mismatch of the sampling NFET, but this is significantly improved by placing the devices in the same line of diffusion and by dummying. The estimated residual RMS timing mismatch is ~0.6ps. The usage of 1.1V NFET for the sampling switches, required for fast sampling edges, would not be possible without the 3b flash ADC, as the top plate signal can reach ±3V during the MSB trial. Analog Devices, Newbury, United Kingdom University of Southampton, Southampton, United Kingdom 3 Analog Devices, Limerick, Ireland 4 now at Vodafone, Newbury, United Kingdom Another key point of the architecture is that the input signal and the RA residue are sampled at the same time, requiring a single quiet time instance during the conversion
Rares Bodnar1,2, Henry Kennedy1, Christopher P Hurrell1, Asif Ahmad1,