A 35.4Gb/s/pin 16Gb GDDR7 with a Low-Power Clocking Architecture and PAM3 IO Circuitry

📋 论文概要

提出一种35.4Gb/s/pin的16Gb GDDR7图形内存，采用低功耗时钟架构和PAM3 IO电路，以满足GPU AI应用和云游戏等高带宽、高能效需求。

💡 主要创新点

• 提出低功耗时钟架构，降低高速运作时的功耗。
• 采用PAM3（三电平脉冲幅度调制）IO电路，在有限带宽下提升数据传输速率。
• 实现35.4Gb/s/pin的业界领先速率，同时保持16Gb大容量。

🏷 关键词

📄 原文摘要

Ji-Hyo Kang, Jinyoup Cha, Seongjin Kim, Youngtaek Kim, Minsoo Park, Gangsik Lee, Keonho Lee, Sanghoon Lee, Gyunam Jeon, Sera Jeong, Yongsuk Joo, Jaehoon Cha, Seonwoo Hwang, Boram Kim, Sangyeon Byeon, Sungkwon Lee, Hyeonyeol Park, Joohwan Cho, Jonghwan Kim SK hynix Semiconductor, Icheon, Korea *Equally Credited Authors (ECAs) The increase in GPU-based AI applications, cloud-based gaming, and video streaming services has driven the need for new a graphics memory that operates at higher bandwidth and power efficiency than existing GDDR6 SDRAM, leading to the introduction of the GDDR7 standard [1]. Since performance degradation due to thermal throttling, power cost, and device reliability are major development considerations in high-power graphics applications, PAM3 signaling is applied on single-ended pins to improve bandwidth and power consumption, while maintaining the clock frequency [2]. However,

👥 作者与机构

Jaehyeok Yang*, Hyeongjun Ko*, Kyunghoon Kim, Hyunsu Park, Jihwan Park,