A 182.3dB FoMs 50MS/s Pipelined-SAR ADC using Cascode Capacitively Degenerated Dynamic Amplifier and MSB Pre-Conversion Technique

📋 论文概要

本文提出了一种采用共源共栅电容退化动态放大器和MSB预转换技术的流水线逐次逼近型模数转换器，在50MS/s采样率下实现了182.3dB的FoMs，解决了传统闭环放大器功耗高和开环放大器线性度不足的问题。

💡 主要创新点

• 提出共源共栅电容退化动态放大器，在开环结构中实现了高增益和高线性度，同时保持低功耗。
• 引入MSB预转换技术，通过提前处理最高有效位来减少后端电路的噪声和线性度要求，进一步提升能效。

🏷 关键词

📄 原文摘要

Information Technology of Peking University, Hangzhou, China 1 2 The residue amplifier (RA) in a pipelined-SAR ADC eases the noise requirement of the back-end stage, making the architecture energy-efficient. However, to achieve high precision, the RA requires both a substantial gain and a high level of linearity. Conventionally, the requirement is met using a closed-loop amplifier [1-2]. However, it consumes a significant amount of power to attain a sufficient bandwidth for settling. To address this problem, the open-loop amplifier has been introduced for energy efficiency [3-4]. Nevertheless, the properties of poor linearity, insufficient gain, and limited output swing restrict its application scenarios. This work presents a 50MS/s pipelined SAR ADC

👥 作者与机构

Zhuoyi Chen1, Linxiao Shen1, Siyuan Ye1, Jihang Gao1, Jie Li1, Jiajia Cui1,

Xinhang Xu1, Yaohui Luan1, Hao Zhang2, Le Ye1,3, Ru Huang1 Peking University, Beijing, China Nano Core Chip Electronic Technology, Hangzhou, China 3 Advanced Institute of