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ISSCC 2024Session 10 · FREQUENCY SYNTHESISClocking & PLLs

A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion

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📋 论文概要

本文提出了一种基于数字锁相环(DPLL)的10GHz FMCW调制器,采用两点调制(TPM)方案,实现了680MHz/μs的快速啁啾斜率和150kHz rms频率误差,旨在提高CMOS FMCW雷达的目标检测空间分辨率和可靠性,支持下一代全自动驾驶汽车。

💡 主要创新点

核心指标
680MHz/μs chirp slope, 150kHz rms frequency error
重要性
发表年份
ISSCC 2024

🏷 关键词

FMCW调制器数字锁相环两点调制啁啾斜率频率误差

📄 原文摘要

Andrea Leonardo Lacaita1, Salvatore Levantino1 Politecnico di Milano, Milan, Italy Infineon Technologies, Villach, Austria *Equally Credited Authors (ECAs) 1 2 Improving the spatial resolution and reliability of target detection in CMOS FMCW radars is essential to facilitate the increased adoption of next generation fully autonomous driving vehicles. In this frame, digital PLLs using the two-point modulation (TPM) scheme (Fig. 10.6.1 top-left) are attractive solutions, thanks to their capability of generating fast and wide-bandwidth (BW) chirp modulations with short retrace time at low power, area, and phase noise [1-3]. Unfortunately, the non-linearity of the digitally controlled oscillator (DCO) degrades chirp linearity, generating significant spurs and triggering the detection of false targets. This issue combined with the existence of a trade-off between linearity and phase noise in the design of DCOs makes it difficult to

👥 作者与机构

Francesco Tesolin*1, Simone Mattia Dartizio*1, Giacomo Castoro1,

Francesco Buccoleri1, Michele Rossoni1, Dmytro Cherniak2, Carlo Samori1,

分类:Clocking & PLLs · 年份:ISSCC 2024