A 48GB 16-High 1280GB/s HBM3E DRAM with All-Around Power TSV and a 6-Phase RDQS Scheme for TSV Area Optimization

📋 论文概要

本文提出一款48GB容量、16层堆叠、带宽1280GB/s的HBM3E DRAM，采用全方位电源TSV（All-Around Power TSV）和6相RDQS方案优化TSV面积，解决高带宽存储器中的功耗和面积挑战。

💡 主要创新点

• 提出All-Around Power TSV结构，通过环绕式电源TSV改善供电效率并节省面积。
• 采用6相读数据选通（6-Phase RDQS）方案，优化TSV布局以减少面积开销。

🏷 关键词

📄 原文摘要

Jae-Hyung Park, Su-Hyun Oh, Yucheon Ju, Chunseok Jeong, Ho Sung Cho, Jaeseung Lee, Tae-Sik Yun, Jin Hee Cho, Sangmuk Oh, Junil Moon, Young-Jun Park, Hong-Seok Choi, In-Keun Kim, Seung Min Yang, Sun-Yeol Kim, Jaemin Jang, Jinwook Kim, Seong-Hee Lee, Younghyun Jeon, Juhyung Park, Tae-Kyun Kim, Dongyoon Ka, Sanghoon Oh, Jinse Kim, Junyeol Jeon, Seonhong Kim, Kyeong Tae Kim, Taeho Kim, Hyeonjin Yang, Dongju Yang, Minseop Lee, Heewoong Song, Dongwook Jang, Junghyun Shin, Hyunsik Kim, Changki Baek, Hajun Jeong, Jongchan Yoon, Seung-Kyun Lim, Kyo Yun Lee, Young Jun Koo, Myeong-Jae Park, Joohwan Cho, Jonghwan Kim SK hynix Semiconductor, Icheon, Korea *Equally Credited Authors (ECAs) With the emergence of large-language models (LLM) and generative AI, which require an enormous amount of model parameters, the required memory bandwidth and capacity for high-end systems is on an unprecedented increase. To meet this need, we present

👥 作者与机构

Jinhyung Lee*, Kyungjun Cho*, Chang Kwon Lee, Yeonho Lee,