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ISSCC 2024Session 14 · DIGITAL TECHNIQUES FOR SYSTEM ADAPTATION, POWER MANAGEMENT AND CLOCKINGDigital Circuits4nm-plus CMOS

A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU

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📋 论文概要

本文提出一种全数字电流传感器,用于4nm-plus八核CPU中每核运行时功耗的精确测量,以支持系统功耗预算管理。该传感器通过数字方式实现,避免了模拟电路的复杂性和面积开销,实现了高精度、低延迟的每核功耗监测。

💡 主要创新点

工艺节点
4nm-plus CMOS
重要性
发表年份
ISSCC 2024

🏷 关键词

全数字电流传感器每核功耗监测系统功耗预算4nm-plus工艺八核CPU

📄 原文摘要

Eric Jia-Wei Fang1, Yuju Cho1, Harry H. Chen1, Ping Kao1, Ericbill Wang1, Hugh Mair2, Shih-An Hwang1 MediaTek, Hsinchu, Taiwan MediaTek, Austin, TX 1 2 The primary focus of flagship smartphones is on the CPU, which utilizes low operating power and high clock speed to deliver competitive performance. To achieve power and performance-efficient capabilities for various computing demands like gaming, browsing, etc., the CPU typically features multiple cores. In one study [1], the CPU scheduling mechanism optimizes the allocation of tasks to each core of the CPU based on predicted available power budgets. Further balancing of power and thermal distribution across the multiple cores is done to ensure sustainable performance. To ensure system stability, power calculation techniques at runtime consider factors of voltage, frequency and leakage, including pessimistic elements such as voltage guard band. As such, an on-die

👥 作者与机构

Chien-Yu Lu1, Bo-Jr Huang1, Min-Chieh Chen1, Ollie Tsai1, Alfred Tsai1,

分类:Digital Circuits · 年份:ISSCC 2024