A 2048×60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia

📋 论文概要

该论文提出了一种在Intel 4工艺上采用PowerVia背面供电技术的2048×60m4 SRAM设计，通过环绕阵列的供电方案降低IR压降并缓解前端信号路由拥塞。

💡 主要创新点

• 首次在SRAM设计中集成PowerVia背面供电技术，利用低电阻背面互连作为供电网络，显著降低IR压降。
• 提出环绕阵列的供电方案（Around-the-Array Power-Delivery），优化供电分布并减少对前端信号路由的干扰。

🏷 关键词

📄 原文摘要

Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl Intel, Hillsboro, OR The ever-increasing demand for energy-efficient computing motivates novel innovations in advanced process technologies. Power through-silicon via (TSV) technology (PowerVia) [1,2] is introduced to utilize low-resistance interconnects on the backside as a power-delivery network (PDN); its benefits include a reduced IR drop in the PDN and relaxed signal-routing congestion on the frontside. By using a technology with PowerVias, a fabricated CPU core achieved >90% standard-cell placement density and demonstrated ~6% higher performance, with ~30% lower IR drop [2]. Incorporation of PowerVias in SRAM array design carries unique tradeoffs, compared to logic design, which require a careful bitcell and array peripheral circuit design to enable an energyefficient and a dense embedded memory. This paper presents a 108Mb high-current

👥 作者与机构

Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park,