A 42GS/s 7b 16nm Massively Time-Interleaved Slope-ADC

📋 论文概要

本文提出了一种基于斜率ADC的大规模时间交织架构，在16nm工艺下实现了42GS/s、7位分辨率的超高速ADC。通过采用极小的斜率子ADC，解决了传统SAR ADC面积大、互连线长的问题，适用于高速数据转换应用。

💡 主要创新点

• 采用斜率ADC替代传统SAR ADC作为子ADC，实现极小面积和高速采样。
• 通过大规模时间交织（42GS/s）实现超高速转换，同时保持低功耗和紧凑布局。
• 利用16nm FinFET工艺优化模拟与数字电路，提升整体效率。

🏷 关键词

📄 原文摘要

resolution of 6 to 8 bits and a sampling speed of several tens of GHz are often required [1–5]. To achieve these extremely high speeds, time-interleaved (TI) ADCs with tens of parallel high-speed channels are commonly used. SAR-based sub-ADCs are a popular choice due to their power-efficient architecture. Although SAR ADCs can be small, the need for a DAC and high-speed logic nevertheless results in a significant total area with long interconnection lines. This work introduces an alternative approach for extreme high-speed ADCs based on the paradigm that a slowspeed but extremely small channel allows for a more efficient conversion per area. By arranging them in a 2-dimensional array, interconnections are minimized, and power burned in parasitics is reduced resulting in an energy-efficient and scalable architecture.

👥 作者与机构

Ewout Martens1, Adam Cooman1, Pratap Renukaswamy1, Shun Nagata2,

Sehoon Park1, Jorge Lagos1, Nereo Markulic1, Jan Craninckx1 1 2 imec, Heverlee, Belgium Sony Semiconductor Solutions, Atsugi, Japan For wireline receivers, ADCs with a