A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS the delay of the DTC based on the LMS calibration method. To satisfy timing constraints, the critical digital blocks are designed with customized logic circuits using low-threshold transistors. The whole HPLL can operate at the minimum voltage of 0.45V (D/VCO at 0.4V) without requiring any voltage booster or bias current.

📋 论文概要

本文提出了一种0.45V供电、0.72mW功耗的2.4GHz无偏置电流分数-N混合锁相环，采用电压模式相位插值器（VPI）实现低电压操作。通过7位分段RDAC（4位二进制R-2R DAC和3位温度计DAC）解决电阻值与线性度的权衡，在28nm CMOS工艺下实现了低噪声和良好匹配。

💡 主要创新点

• 提出无偏置电流的分数-N混合PLL架构，消除传统PLL中的偏置电流源，降低功耗和电压要求。
• 采用电压模式相位插值器（VPI），利用无源电阻和开关实现低电压下的高线性度和低噪声。
• 使用7位分段RDAC（R-2R+温度计）优化电阻值与线性度，且等效输出电阻恒定，简化设计。

🏷 关键词

📄 原文摘要

Jiahao Zhao, Woogeun Rhee, Zhihua Wang Figure 14.7.3 shows the structure and properties of the proposed VPI. A 7b segmented RDAC combines a 4b binary R-2R DAC and a 3b thermometer DAC to tackle the tradeoff between resistor value and linearity. Each bit is driven by a switch to select one of two references, VREFP and VREFN. With only resistors and simple switches used in the RDAC, this simple and passive-intensive structure achieves better matching and low noise contribution under ULV operation. The equivalent output resistance of the RDAC has a constant value across all control codes to avoid the variation of poles in the PLL, and the output voltage is changed by the control codes to realize voltage interpolation. The full scale of the RDAC output voltage can be tuned by the voltage regulator to adjust the PLL bandwidth. In the noise model, the RDAC has the same effect as the LPF resistor.

👥 作者与机构

Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han,