A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with

📋 论文概要

本文提出了一款采用1a-nm工艺、1.05V供电、10.5Gb/s/pin数据速率的16Gb LPDDR5 Turbo DRAM。通过引入WCK校正策略、电压偏移校准接收器和寄生电容优化技术，解决了高速接口中的时序和信号完整性挑战。

💡 主要创新点

• 提出WCK校正策略，用于补偿时钟路径失配，提升高速数据采样精度。
• 设计电压偏移校准接收器，动态调整接收阈值，降低工艺偏差影响。
• 利用寄生电容优化技术，改善信号完整性和功耗效率。

🏷 关键词

📄 原文摘要

Yangho Seo*, Jihee Choi*, Sunki Cho, Hyunwook Han, Wonjong Kim, Gyeongha Ryu, Jungil Ahn, Younga Cho, Sungphil Choi, Seohee Lee, Wooju Lee, Chaehyuk Lee, Kiup Kim, Seongseop Lee, Sangbeom Park, Minjun Choi, Sungwoo Lee, Mino Kim, Taekyun Shin, Hyeongsoo Jeong, Hyunseung Kim, Houk Song, Yunsuk Hong, Seokju Yoon, Giwook Park, Hokeun You, Changkyu Choi, Hae-Kang Jung, Joohwan Cho, Jonghwan Kim SK hynix, Icheon, Korea *Equally Credited Authors (ECAs) The LPDDR product family originally sought to minimize power consumption. As the LPDDR5X is released with a 33% increase in maximum operating speed, low-power and high-speed operations have become essential [1]. Moreover, expanding virtual space (AR, XR) and the artificial intelligence industry have accelerated demand for high-speed and low-power mobile DRAM products. Therefore, guaranteeing higher IO speed has become a significant concern in designing DRAM. This paper proposes a WCK correction

👥 作者与机构

WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver, and Parasitic Capacitance Reduction