A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with

📋 论文概要

该论文提出了一种基于62.5MHz参考的7.5GHz次谐波注入锁定时钟乘法器，通过优化注入强度实现了低相位噪声和低参考杂散。解决了传统注入锁定时钟乘法器中参考杂散随注入强度和倍频因子增大的问题。

💡 主要创新点

• 实现了7.5GHz输出频率下-259.7dB FoMJ的优异相位噪声性能
• 在62.5MHz参考下达到-56.6dBc的低参考杂散，抑制了注入锁定中的杂散问题

🏷 关键词

📄 原文摘要

multipliers, as it can lower the phase noise of a VCO beyond what can be achieved by the PLL loop bandwidth. The amount of phase-noise reduction depends on the injection strength and reaches a maximum when the clock edge of the reference clock fully replaces that of the VCO [1]. However, one drawback of the SIL clock multiplier (SILCM) is the reference spur, which increases with the injection strength and the multiplication factor (N). For ring oscillator-based clock multipliers, the injection strength can be maximized by using a multiplying delay-locked loop (MDLL), which fully supplants the output clock edge by the reference. Since a ring oscillator has a square-wave-like waveform, a clock edge replacement causes little distortion to the waveform, and a seamless replacement of the

👥 作者与机构

a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference, Spur

Hangil Choi, SeongHwan Cho Korea Advanced Institute of Science and Technology, Daejeon, Korea Subharmonic injection locking (SIL) is a popular technique for low-jitter clock