e-Chimera: A Scalable SRAM-Based Ising Macro with Enhanced-Chimera Topology for Solving Combinatorial Optimization Problems Within Memory

📋 论文概要

本文提出了一种基于SRAM的Ising计算宏e-Chimera，采用增强型Chimera拓扑结构，旨在解决组合优化问题。相比传统量子退火器，该设计在常温下运行，并具备可扩展性，克服了量子计算对极低温环境的依赖。

💡 主要创新点

• 首次在SRAM宏中实现增强型Chimera拓扑，提高了Ising模型的连接度与计算能力。
• 采用全数字CMOS工艺设计，无需超导量子比特，实现了常温可扩展的Ising计算加速器。

🏷 关键词

📄 原文摘要

Ising machines, hardware accelerators based on the Ising model, have recently gained interest as alternative computers for solving combinatorial optimization problems (COPs) in various industrial fields with practical applications such as logistics, supply chain optimization, and financial portfolio management. One of the early implementations of the Ising machines is a quantum annealer [1] that is built with superconducting qubits operating at an extremely low operating temperature (15 - 20mK). The quantum machine implemented 2048 qubits that are connected in a Chimera graph topology with a degree of 6, which indicates the number of interactions per qubit, where eight qubits are connected in a local bipartite graph with two separate groups – i.e., a 4×4 fully connected qubit structure with no connection between qubits in the same group of four qubits. CMOS-based ASIC Ising accelerators [2-5] have been developed to overcome the

👥 作者与机构

Jooyoung Bae, Chaeyun Shim, Bongjin Kim

University of California, Santa Barbara, CA