A 28nm 83.23TFLOPS/W POSIT-Based Compute-in-Memory Macro for High-Accuracy AI Applications and denotes early 01 or 10 change. It uses XOR and a leading-one detector if RA/RB with different signs. BRPU reduces the regime processing energy by 68%.

📋 论文概要

本文提出了一种基于POSIT数据格式的存算一体宏单元，采用28nm CMOS工艺，实现了83.23TFLOPS/W的高能效，适用于高精度AI应用。通过CPCS架构和4b计算单元的多模式设计，解决了传统存算一体在精度和利用率上的不足。

💡 主要创新点

• 首次在存算一体宏中采用POSIT数值格式，相比传统浮点或定点格式，在保证高精度的同时提升了计算能效。
• 提出CPCS（Critical-Path Computing Structure）架构，通过将48b行分为12个4b计算单元，并支持三种工作模式，显著提高了阵列利用率。

🏷 关键词

📄 原文摘要

Zhiheng Yue1, Huiming Han1, Shaojun Wei1, Yang Hu1, Shouyi Yin1,2 Figure 34.1.4 depicts the CPCS, increasing the CIM array utilization. The CPCS CIM core consists of an 8×48 CIM array, a load controller, a critical-bit computing unit, and a 3:8 decoder. The 48b cell of each row is separated into 12 CIM units, each containing 4 CIM cells. The 4b CIM unit has 3 work modes: (1) when storing 3b W[2:0], it receive A[n]|A[n+2] in each cycle to get P[2:0] = W × (A[n]|A[n+2]). A dual-bit MAC unit uses P[2:0] to obtain O = W × A[n] + W × A[n+2]. If A[n+2] / A[n] = 00 or 01 then O = P[2:0]. If A[n+2] / A[n] = 10 then O = P[2:0]<<2. Otherwise, O = P[2:0] + P[2:0]<<2 = [0,0,P2,P1,P0] + [P2,P1,P0,0,0]. The dual-bit MAC unit gets O by computing 3b S[3:0] = [0,0,P2] + [P2,P1,P0] and concatenates [P1,P0]. The computation of S[1] consumes the largest number of transistors, defined as a critical bit, where S[1] = W[P] = W[1] ^ (W[0]

👥 作者与机构

Yang Wang1, Xiaolong Yang1, Yubin Qin1, Zhiren Zhao1, Ruiqi Guo1,