Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

📋 论文概要

本文提出了一种自启用的写辅助单元（SEWACs），用于电阻主导工艺节点下的高密度SRAM。该方案在不增加额外哑单元的情况下提高了写辅助能力，解决了传统写辅助电路面积开销大和位交错需求导致的额外面积问题。

💡 主要创新点

• 提出自启用写辅助单元（SEWACs），无需额外哑单元即可实现位交错，降低了面积开销。
• 通过增加辅助单元提升了可容忍的RBL_cell（位线电阻容忍度），适用于高密度SRAM。
• 相比传统写辅助电路（W-ACs），SEWACs在减少面积的同时保持或提升了写辅助性能。

🏷 关键词

📄 原文摘要

proposed schemes, according to the number of rows per BL (RPB). As the RPB decreases, the proportion of the write assist circuits to the bit cells becomes larger; thus, the area overhead increases. On the other hand, increasing RPB reduces the tolerable RBL_cell. However, cell-compatible schemes can increase the tolerable RBL_cell by adding assist cells. As shown in Fig. 15.4.5 (top right), SEWACs do not require additional dummy cells for bit-interleaving, while W-ACs increase the area overhead due to their requirement of dummy cells for bit-interleaving. The proposed SEWACs achieve almost the same writability as W-ACs and the smallest area overhead without timing control for a 4:1 bit-interleaved structure. 2 For applications where a significant amount of data is processed within a limited area,

👥 作者与机构

Minjune Yeo1, Keonhee Cho1, Giseok Kim1, Won Joon Jo1, Jisang Oh1,

Sekeon Kim1, Kyeongrim Baek1, Sungho Park1, Seung Jae Yei1, Seong-Ook Jung1,2 Yonsei University, Seoul, Korea Articron, Ansan, Korea 1 area overhead, for the previous and