Racing Down the Slopes of Moore’s Law Bram Nauta

📋 论文概要

本文回顾了摩尔定律的发展历程，指出其缩放速度放缓，但晶体管数量和成本/功能仍通过3D集成进步。作者提出应重新考虑模拟与数字信号处理的设计方式，强调在高信噪比下数字处理更节能。

💡 主要创新点

• 指出摩尔定律在处理器时钟速度和RF晶体管速度缩放上停滞，数字门功耗效率可能面临瓶颈。
• 强调高信噪比应用中数字信号处理比模拟更高效，建议重新设计信号处理架构。
• 倡导利用3D集成技术继续推进晶体管密度和成本效益，改变传统设计思维。

🏷 关键词

📄 原文摘要

Since its inception, Moore’s Law has been the driving force for IC design. Although during the first decade, “everything” seemed to be better, however, we lost the scaling of processor clock speed and RF transistor speed, and now it looks as if power efficiency of digital gates will stall. What remains is scaling in transistor count and cost-perfunction, thanks to 3D integration. Thus, this is an excellent moment to reconsider how we design for analog and digital signal processing. The higher the required signal-to-noise ratio (SNR), the more powerefficient digital signal processing is compared to analog. Pure analog processing remains more efficient only for ~30dB SNR or less. In the case of digital processing, the conversion from analog to digital should therefore be made as early in the signal chain as possible. Thanks to the figure-of-merit race, analog-to-digital converters (ADCs) have experienced a tremendous win in power efficiency. However, these ADCs require a large

👥 作者与机构

University of Twente, Enschede, The Netherlands.