A 3D integrated Prototype System-on-Chip for Augmented Reality Applications Using Face-to-Face Wafer Bonded 7nm Logic at <2μm Pitch with up to 40% Energy Reduction at Iso-Area Footprint The 3D clock forwarding methodology enables extension of the SMEM from 16 to 32MB without expanding the original area footprint (4.6MB/mm2). The SMEM access energy is measured for both top die and bottom die banks to be 1.84 and 1.99pJ/B, respectively, at nominal frequency of 500MHz (Fig. 11.2.3) with 0.15pJ/B attributed to the inter-die access. From post-layout RC extracted simulations, only 0.03pJ/B of the access energy is attributed to the 3D interconnects. While on-die temperatures may be a concern for

📋 论文概要

该论文提出了一款面向增强现实应用的3D集成原型系统芯片，采用面对面晶圆键合7nm逻辑工艺，解决了AR产品对高性能、低功耗和小面积的需求。通过集成包含1K处理单元的机器学习加速器，实现了高效处理ML、NN和ISP任务。

💡 主要创新点

• 采用3D面对面晶圆键合技术实现7nm逻辑与传感器/存储器的异构集成，大幅提升芯片集成度与能效。
• 定制化设计包含1K处理单元的机器学习加速器，针对AR应用优化了性能与功耗平衡。
• 通过紧凑的封装和面积优化，满足AR产品对小型化与低功耗的严格要求。

🏷 关键词

📄 原文摘要

Tony F. Wu, Huichu Liu, H. Ekin Sumbul, Lita Yang, Dipti Baheti, Jeremy Coriell, William Koven, Anu Krishnan, Mohit Mittal, Matheus Trevisan Moreira, Max Waugaman, Laurent Ye, Edith Beigné As a case study, we augmented a standalone ML accelerator consisting of 1K processing Meta, Sunnyvale, CA Augmented reality (AR) products require energy-efficient systems-on-chip (SoCs) for machine learning (ML), neural networks (NNs), and image signal processing (ISP) applications [1]. These SoCs must be high-performance, yet low power with compact form factors. They are heavily constrained by the area footprint, while the third dimension is usually left with ample space. Moreover, frequent access to off-chip memories can be prohibitively expensive in terms of latency and energy for AR devices. Fortunately, recent advances in 3D integration allow integration of additional logic and memory into the SoC without area footprint cost. In particular, face-to-face (F2F) stacking with hybrid bonding

👥 作者与机构

3D stacked SoCs designed for high performance computing, they are not significant for, those designed for AR applications (e.g., max on-die temperature of 29°C for our chip).