A/mm2 Scalable Distributed All-Digital 6×6 Dot-LDOs Featuring Freely Linkable Current-Sharing Network: A Fine-Grained On-Chip Power Delivery Solution in 28nm CMOS

📄 原文摘要

architecture is emerging as a solution for on-chip power delivery [1-6]. Multiple digital LDO (D-LDO) units cooperate inside this framework to regulate supply voltage via a shared power grid network. By evenly dispersing the load current among the D-LDO units, this point-ofload regulation helps considerably in both reducing thermal intensity and mitigating the IR drop brought on by parasitic resistance (RG) within the power grid. In line with this technical direction, as shown at the top of Fig. 14.10.1, a finer-grained distribution, leveraging a greater number of smaller current-capacity D-LDOs, may be a more desirable way to ease the thermal budget and further minimize RG attributed to the shorter distances between D-LDOs. However, a smaller RG leads to higher sensitivity to the

👥 作者与机构

Yong-Jin Lee1,2, Woojin Jang1,2, Hong-Hyun Bae1, Jeong-Hyun Cho1, Hyun-Sik Kim1

Korea Advanced Institute of Science and Technology, Daejeon, Korea Samsung Electronics, Hwaseong, Korea 1 2 As modern SoCs become more power-intensive, the distributed LDO