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ISSCC 2024Session 30 · DOMAIN-SPECIFIC COMPUTING AND DIGITAL ACCELERATORSDigital Circuits

A Fully Integrated Annealing Processor for Large-Scale Autonomous Navigation Optimization selectors arranged in two stages, reducing the critical path by 85% compared to the design with a 1024b selector. An additional LFSR is included to ensure that the resulting distribution reaches uniformity.

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📋 论文概要

该论文提出了一种全集成退火处理器,用于大规模自主导航优化中的聚类问题。通过平衡集群大小和将二维聚类计算映射到一维处理单元阵列,减少了内存访问和数据冲突,实现了高效的聚类优化。

💡 主要创新点

重要性
发表年份
ISSCC 2024

🏷 关键词

退火处理器自主导航优化聚类计算处理单元阵列

📄 原文摘要

In this work, the sizes of the clusters can be balanced by limiting the number of stations in a cluster. Memory access to the locations of stations can be reduced by mapping computations for clustering in a 2D array onto a 1D Processing Unit (PU) array. The PU Array is composed of 32 PUs to calculate and accumulate the minimal distance (using the broadcast data from the Cluster Size Arbiter) in a serial-in serial-out manner. The Summation Updater then updates a centroid and its cluster’s size. This reduces the number of data conflicts by 87%. The Silhouette Score, with a value between +1 and -1, is used as the metric to evaluate the clustering performance. A higher Silhouette Score indicates better clustering performance, and the proposed architecture improves the mean Silhouette Score by 0.47 compared to the baseline design, in which a PU array is deployed in a parallel-in manner without the Cluster Size Arbiter.

👥 作者与机构

Yi-Chen Chu, Yu-Cheng Lin, Yu-Chen Lo, Chia-Hsiang Yang, Figure 30.4.5 shows the design details of the Clustering Unit and the multichip system.

分类:Digital Circuits · 年份:ISSCC 2024