A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process Figure 13.2.4(a) shows a conceptual DRAM read block diagram. The DLL matches the skew of CLK and DQS. The quadrature-error corrector (QEC) matches the 4-phase skew.

📋 论文概要

该论文提出了一种32Gb、8.0Gb/s/pin的DDR5 SDRAM，采用对称马赛克架构，在第五代10nm DRAM工艺上实现。为了解决DLL代码变化导致的确定性抖动和四相偏移问题，设计了一种混合开环/闭环DCC，显著降低了四相偏移。

💡 主要创新点

• 提出对称马赛克架构，实现高密度高带宽DDR5 SDRAM。
• 采用混合开环/闭环DCC技术，减少DLL引起的确定性抖动和四相偏移。
• 在第五代10nm DRAM工艺上实现32Gb容量和8.0Gb/s/pin速率。

🏷 关键词

📄 原文摘要

does not change properly or shows slow response, a deterministic jitter is generated. In our design, an open-loop DCC, shown in Fig. 13.2.4(b), is added before the QEC. Dutycycle distortion, from DLL code variation, is not visible while the burden on the QEC and the resulting deterministic jitter is reduced. Figure 13.2.4(c) shows simulated DLL-output quad-skew variation with and without the open loop DCC. The quad-skew variation is decreased from 3.24 to 1.83ps by this hybrid opened-/closed-loop approach. Ikjoon Choi, Seunghwan Hong, Kihyun Kim, Jeong-Sik Hwang, Seunghan Woo, Young-Sang Kim, Cheong-Ryong Cho, Eun-Young Lee, Hun-Jae Lee, Min-Su Jung, Hee-Yun Jung, ju-Seong Hwang, Junsub Yoon, Wonmook Lim, Hyeong-Jin Yoo, Won-Ki Lee, Jung-Kyun Oh, Dong-Su Lee, Jong-Eun Lee, Jun-Hyung Kim, Young-Kwan Kim, Su-Jin Park, Byung-Kyu Ho, Byong-Wook Na, Hye-In Choi, Chung-Ki Lee, Soo-Jung Lee, Hyunsung Shin,

👥 作者与机构

Previously, the output of the DLL goes directly into the QEC[1]. The code change of the, DLL due to any external factor causes duty-cycle distortion in the DLL, which lead to 4phase skew; so, the QEC should respond immediately and correct it. If the QEC code