A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture

📋 论文概要

该论文提出了一种基于3nm FinFET工艺的双泵浦伪双端口SRAM，采用折叠位线多存储体架构，实现了4.3GHz工作频率和21.1Mb/mm2的高密度。通过时序切片双泵浦技术，利用单端口6T单元实现连续读写操作，解决了高性能计算中双端口SRAM的速度与密度挑战。

💡 主要创新点

• 提出折叠位线多存储体架构，有效降低位线负载和延迟，支持高频操作。
• 采用双泵浦技术，在单端口6T单元上实现伪双端口读写，兼顾高密度与高速度。
• 在3nm FinFET工艺上实现4.3GHz频率和21.1Mb/mm2密度，达到业界领先水平。

🏷 关键词

📄 原文摘要

2-port (dual-port) SRAM is one of the major challenges to achieve maximum frequency (fMAX) operation and memory cell density for high-performance computing (HPC) applications: such as massively parallel-processing, imaging, video graphics, and deep-learning AI processors. In addition to high-speed operation, area scaling is also important, because embedded SRAM capacity tends to increase with technology nodes, occupying a huge portion in recent SoC. Timing-sliced doublepumped 2-port SRAMs, using a typical single-port (SP) 6T bit cell, have been proposed [1-4]; thereby, enabling consecutive read and write operations. Though it is limited for both ports to synchronize to one clock phase and there is a certain cycle time penalty

👥 作者与机构

Masaru Haraguchi1, Yorinobu Fujino1, Yoshisato Yokoyama1,

Ming-Hung Chang2, Yu-Hao Hsu2, Hong-Chen Cheng2, Koji Nii1, Yih Wang2, Tsung-Yung Jonathan Chang2 TSMC Design Technology Japan, Yokohama, Japan TSMC, Hsinchu, Taiwan 1 2 An embedded